• Journal of Digital Contents Society
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• v.9 no.4
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• pp.717-723
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• 2008

Many of the domestic PC manufactures and professional PC repair shops are suffering from lack of efficient diagnostic database systems or CAD tools for diagnosis and repair of PCs. In order to solve this problem, a new diagnostic database system for PC maintenance and repair is presented in this paper. We can perform accurate and rapid diagnosis for the PCs with software and hardware troubles by using proposed database system and thus the number of customers who are satisfied with service results are to be increased. Furthermore our research outputs make it possible the experts in PC repair field accumulate maintenance techniques and enhance the reliability of performance evaluated by customers.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.12
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• pp.1-10
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• 1999

In this paper, we analyzed the radiation patterns of a monopole antenna mounted on the complex structures by using FDTD method associated with 3-D PML absorbing boundary condition. In order to validate the proposed FDTD code, the radiation patterns of monopole antenna mounted on cylinders and spheres were compared with the exact solutions of $Carter^{[1]}$ and $Harrington^{[2]}$. For all case considered, the predicted radiation pattern exhibited excellent agreement with exact solution. To be able to model the more complex structures, the proposed FDTD methods are combined with BRL-CAD. And this procedures is applied to predict the radiation patterns of a wire antenna attached to the top of a Blackhawk helicopter.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.8
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• pp.514-523
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• 2006

In this paper we propose an extended interleaving technique to improve a detailed placement. The existing row-based interleaving technique allows cells to move only within a row and it can be applied when there is no space between cells. The proposed extended-interleaving technique releases such constraints so that cells can move along with a vertical line parallel to a y-axis and space between cells is properly handled. Converged detailed-placements by a mature CAD tool have been improved by the proposed interleaving technique by 9.5% on average in half-perimeter wire length.

• Proceedings of the Korea Society for Simulation Conference
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• 2001.05a
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• pp.82-87
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• 2001

In this paper we described the generation method of interface logic which can be replace between IP and IP handshaking signal with asynchronous logic circuit. Especially, we suggest the new \"Waveform Conversion Algorithm : Wave2VHDL\", if only mixed asynchronous timing waveform suggested which level type input and pulse type input for handshaking, we can convert waveform to flowchart and then replaced with VHDL code according to converted flowchart. Also, we assure that asynchronous electronic circuits for IP interface are generated by applying extracted VHDL source code from suggested algorithm to conventional domestic/abroad CAD Tool, and then we proved that coincidence simulation result and suggested timing diagram.g diagram.

• Journal of the Korean Society for Precision Engineering
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• v.22 no.1
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• pp.26-31
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• 2005

소비자가 주도하는 현대의 시장에서 제품의 복잡성은 점점 더 커지고, 제품 개발 활동은 지리적으로 분산되어 수행되는 경향이 확산되고 있다. 이러한 환경에서 요구되는 설계 개발 툴로서의 지능형 설계 시스템은 종래의 CAD 시스템보다 다양한 기능을 가져야 하고, 도면이나 문서와 같은 전통적인 정보보다 다양하고 고도화된 정보를 취급할 수 있어야 한다. 이와 같이 제품이나 부품의 형상 외에도 설계 의도와 규칙, 지식 등을 포함하여 기능과 거동 및 구조를 표현할 수 있는 플랫폼을 설계 저장소라 한다. 조립 제품을 대상으로 하는 설계 저장소(NIST Design Repository)와 소프트웨어를 대상으로 하는 설계 저장소(SPOOL Design Repository)의 개발 사례를 들어, 설계 저장소가 설계의 지능화에 어떻게 기여할 수 있으며 얼마나 중요한 지를 소개하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.11a
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• pp.147-150
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• 2005

본 논문에서는 협동적 제품 개발 환경에서 제품 설계 데이터와 제품 내의 객체 정보를 매칭하고 영상 기반에서 공학 데이터를 검색하기 위한 목적으로 영상 내의 객체의 각 영역을 분할 하고자 한다. 제품 설계시 생성 과정에서 CAD 툴 등으로부터 생성되는 영상은 객체 화소값의 차이가 적고 생산환경에 맞게 실시간으로 정보를 제공 할 수 있어야 한다. 위와 같은 두 가지 사항을 해결하기 위해, 전처리 과정이 없이 객체 내의 각 부분 정보를 알 수 있는 에지 기반 라벨링(Edge_Based Labeling) 기법을 제안한다.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.96-106
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• 2014

Previous academic research on FPGA tools has relied on simple imaginary models for the targeting architecture. As the first step to overcome such restriction, the issues on analytic placement and legalization which are applied to commercial FPGAs have been brought up, and several techniques to remedy them are presented, and evaluated. First of all, the center of gravity of the placed cells may be far displaced from the center of the chip during analytic placement. A function is proposed to be added to the objective function for minimizing this displacement. And then, the density map is expanded into multiple layers to accurately calculate the density distribution for each of the cell types. Early fixation is also proposed for the memory blocks which can be placed at limited sites in small numbers. Since two flip-flops share control pins in a slice, a compatibility constraint is introduced during legalization. Pre-packing compatible flip-flops is proposed as a proactive step. The proposed techniques are implemented on the K-FPGA fabric evaluation framework in which commercial architectures can be precisely modeled, and modified for enhancement, and validated on twelve industrial strength examples. The placement results show that the proposed techniques have reduced the wire length by 22%, and the slice usage by 5% on average. This research is expected to be a development basis of the optimization CAD tools for new as well as the state-of-the-art FPGA architectures.

• Spatial Information Research
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• v.18 no.5
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• pp.47-54
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• 2010

Until recently, GIS technology was mainly based on 2D for disaster management. Necessity of 3D spatial information came to the fore with a speedy and accurate response system in disaster management. However, most fire-fighting facilities presently use CAD with 2D formation, Image drawings, and conception of construction data's formation. It is not about the drawings in map production. It's about varieties of construction ways or contents. In this study, we are proposing the ways on analyzing the existing disaster management targets for 2D technology drawings, designing the 3D spatial information data model, and transforming the effective 3D spatial information into algorithm and dimension spatial information construction for easily building on mass 2D architectural drawings to 3D spatial information effectively in disaster management. We can maxim ize efficient construction time and expenses. Then what is proposed in this study about constructing 3D spatial information for manual work, and it's significance for improving decisive decisions and utilizing the tasks to prevent, prepare, respond and restore steps in disaster management.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.3
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• pp.72-77
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• 2017

This paper focuses on the development of a supporting S/W tool for the automated design of an automotive press trim die. To define the die design process based on automation, we analyze the press die design process of the current industry and group repetitive works in the 3D modeling process. The proposed system consists of two modules, namely the template models of the trim steel parts and UI function for their auto-positioning. Four kinds of template models are developed to adapt to various situations and the rules of the interaction formula which are used for checking and correcting the directions of the datum point, datum curve, datum plane are implemented to eliminate errors. The system was developed using CATIA Knowledgeware, CAA(CATIA SDK) and Visual C++, in order for it to function as a plug-in module of CATIA V5, which is one of the major 3D CAD systems in the manufacturing industry. The developed system was tested by applying it to various panels of current automobiles and the results showed that it reduces the time-cost by 74% compared to the traditional method.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.12
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• pp.41-50
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• 1999

In this paper, the new VLSI architecture of a reconstruction filter for morphological image segmentation is proposed. The filter, based on the $h_{max}$ operation, simplifies the interior of each region while preserving the boundary information. The proposed architecture adopts a partitioned memory structure and an efficient image scanning strategy to reduce the operations. The proposed memory partitioning scheme makes it possible that every data required for processing can be read from each memory at a time, resulting in parallel data processing. By the extended connectivity consideration, the operation is much decreased because more simplification is achieved in scanning stage. The selective raster scan strategy endows the satisfactory noise removal capability with negligible hardware complexity increase. The proposed architecture is designed using VHDL, and functional evaluation is performed by the CAD tool, Mentor. The experiment results show that the proposed architecture can simplify image profile with less than 18% operations of the conventional method.