• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.1
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• pp.64-74
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• 2008

It is well-known that the coding efficiency of CABAC which is one of the entropy coding methods in H.264/AVC is lower than that of CAVLC at high bitrate in intra coding, even if CABAC shows higher coding efficiency than CAVLC. Therefore, for high quality video application, this paper proposes new binarization methods about the quantized DCT coefficients that are partitioned into four regions such that CABAC shows similar coding efficiency to CAVLC at high bitrate. The proposed binarization methods consist of separate binarization tables about the four partitioned DCT coefficients considering the statistical characteristics of the quantized DCT coefficients. The proposed binarizaton method for the quantized DCT coefficients shows higher coding efficiency than CABAC in H.264/AVC and shows very similar result to CAVLC at high bitrate.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2013.06a
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• pp.278-279
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• 2013

최근에 완료된 HEVC(High Efficiency Video Coding) 비디오 압축 표준은 H.264/AVC에 비해 2배 이상 향상된 압축 효율을 제공한다. 현재 진행 중인 HEVC 확장 (extension) 작업에서는 손실 및 무손실 부호화에서 4:2:2 및 4:4:4 색차 포맷과 최대 12비트 깊이를 지원하는 고급 프로파일을 개발하고 있다. 현재까지 개발된 HEVC의 CABAC(Context-based Adaptive Binary Arithmetic Coding)은 손실 부호화 환경에 적합하게 설계되었기 때문에 무손실 부호화 환경에서 최적의 부호화 성능을 제공하지 못한다. 본 논문에서는 4:4:4 색차 포맷 영상의 무손실 화면내 부호화 환경에서 잔여 신호의 통계적 특성을 고려한 향상된 CABAC 잔여 데이터 부호화 방법을 제안한다. 실험 결과를 통해, 본 논문에서 제안하는 향상된 CABAC 방법이 무손실 화면내 부호화에서 기존의 CABAC 방법에 비해 평균 약 2.41% 의 비트 수를 감소시키는 것을 확인했다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.34-40
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• 2010

This paper proposes an efficient CABAC encoder to reduce syntax element storage in H.264/AVC entropy coding. In the proposed architecture, all blocks are designed in dedicated hardware, so it performs fast processing without programmable processors. Context modeler of CABAC encoder requires the neighbor block data. However it requires impractically huge memory size if the neighbor block data is directly stored without proper processing. Therefore, this paper proposes an effective method of storing the neighbor block data to decrease memory size. The proposed CABAC encoder has 35,463 gates in 0.18um standard cell library. It operates at maximum speed of 180MHz and its throughput is about 1 cycle per input symbol.

• Journal of IKEEE
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• v.21 no.3
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• pp.280-283
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• 2017

HEVC (high efficiency video coding) exploits CABAC (context-based adaptive binary arithmetic coding) for entropy coding, where a context model estimates the probability for each syntax element. In this paper, a context modeler was designed and implemented for CABAC decoding. lookup table was used to reduce computation and to increase speed. 12 simulations for HEVC standard test sequences and encoder configurations were performed, and the context modeler was verified to perform correction operations. The designed context modeler was synthesized in 0.18um technology. Maximum frequency, maximum throughput, and gate count are 200 MHz, 200 Mbin/s, and 29,268 gates, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.155-164
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• 2015

This paper describes a design and implementation of CABAC decoder, which would handle HEVC syntax elements in adaptively pipelined-parallel computation manner. Even though CABAC offers the high compression rate, it is limited in decoding performance due to context-based sequential computation, and strong data dependency between context models, as well as decoding procedure bin by bin. In order to enhance the decoding computation of HEVC CABAC, the flag-type syntax elements are adaptively pipelined by precomputing consecutive flag-type ones; and multi-bin syntax elements are decoded by processing bins in parallel up to three. Further, in order to accelerate Binary Arithmetic Decoder by reducing the critical path delay, the update and renormalization of context modeling are precomputed parallel for the cases of LPS as well as MPS, and then the context modeling renewal is selected by the precedent decoding result. It is simulated that the new HEVC CABAC architecture could achieve the max. performance of 1.01 bins/cycle, which is two times faster with respect to the conventional approach. In ASIC design with 65nm library, the CABAC architecture would handle 224 Mbins/sec, which could decode QFHD HEVC video data in real time.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.401-404
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• 2016

This paper proposes entropy coding method of HEVC CABAC Encoder for efficient hardware architecture. The Binary Arithmetic Encoder requires data dependency at each step, which is difficult to be operated in a fast. Proposed Binary Arithmetic Encoder is designed 4 stage pipeline to quickly process the input value bin. According to bin approach, either MPS or LPS is selected and the binary arithmetic encoding is performed. Critical path caused by repeated operation is reduced by using the LUT and designed as a shift operation which decreases hardware size and not using memory. The proposed Binary Arithmetic Encoder of CABAC is designed using Verilog-HDL and it was implemented in 65nm technology. Its gate count is 3.17k and operating speed is 1.53GHz.

• Journal of IKEEE
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• v.20 no.4
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• pp.435-438
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• 2016

HEVC CABAC binary arithmetic decoder operates in three decoding modes i.e. regular, bypass, and termination modes, where their decoding operations and time differ a lot. Furthermore, when renormalization occurs, its internal feedback loop induces large delay. In this paper, a binary arithmetic decoder was designed to solve this problem. In advance, it checks all range values with possible renormalization. When renormalization occurs, it immediately updates range value and finishes all calculation in a cycle. When implemented in 0.18 um process technology, its maximum operating frequency and gate counts are 215 MHz and 5,423 gates, respectively.

• Journal of IKEEE
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• v.18 no.3
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• pp.356-361
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• 2014

This paper proposes hardware architecture of HEVC (high efficiency video coding) CABAC (context-based adaptive binary arithmetic coding) binarizer. The proposed binarizer was designed and implemented as an independent module that can be integrated into HEVC CABAC encoder. It generates each bin string of each syntax element in a single cycle. It consists of controller module, TU (truncated unary binarization) module, TR (truncated Rice binarization) module, FL (fixed length binarization) module, EGK (k-th order exp-Golomb coding) module, CALR (coeff_abs_level_remaining) module, QP Delta (cu_qp_delta_abs) module, Intra Pred (intra_chroma_pred_mode) module, Inter Pred (inter_pred_idc) module, and Part Mode (part_mode) module. The proposed binarizer was designed in Verilog HDL, and it was implemented in 45 nm technology. Its operating speed, gate count, and power consumption are 200 MHz, 1,678 gates, and 50 uW, respectively.

• IEIE Transactions on Smart Processing and Computing
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• v.6 no.4
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• pp.292-298
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• 2017

The complexity of image compression algorithms has increased in order to improve image compression efficiency. One way to resolve high computational complexity is parallel processing. However, entropy coding, which is lossless compression, does not fit into the parallel processing form because of the correlation between consecutive symbols. This paper proposes a new application-specific instruction set processor (ASIP) platform by adding new context-adaptive binary arithmetic coding (CABAC) instructions to the existing platform to quickly process a variety of entropy coding. The newly added instructions work without conflicts with all other existing instructions of the platform, providing the flexibility to handle many coding standards with fast processing speeds. CABAC software is implemented for High Efficiency Video Coding (HEVC) and the performance of the proposed ASIP platform was verified with a field programmable gate array simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.61-68
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• 2008

In this paper, we propose an efficient hardware architecture and algorithm to increase an encoding process rate and implement a hardware for CABAC (Context Adaptive Binary Arithmetic Coding) which is used with one of the entropy coding ways for the latest video compression technique, H.264/AVC (Advanced Video Coding). CABAC typically provides a better high compression performance maximum 15% compared with CAVLC. However, the complexity of operation of CABAC is significantly higher than the CAVLC. Because of complicated data dependency during the encoding process, the complexity of operation is higher. Therefore, various architectures were proposed to reduce an amount of operation. However, they have still latency on account of complicated data dependency. The proposed architecture has two techniques to implement efficient pipeline architecture. The one is quick calculation of 7, 8th bits used to calculate a probability is the first step in Binary arithmetic coding. The other is one step reduced pipeline arcbitecture when the type of the encoded symbols is MPS. By adopting these two techniques, the required processing time was reduced about 27-29% compared with previous architectures. It is designed in a hardware description language and total logic gate count is 19K using 0.18um standard cell library.