• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.149-160
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• 1997

This paper is concerned with the problem of speaker-adaptive speech synthes is method using a mapped codebook designed by fuzzy mapping on FLVQ (Fuzzy Learning Vector Quantization). The FLVQ is used to design both input and reference speaker's codebook. This algorithm is incorporated fuzzy membership function into the LVQ(learning vector quantization) networks. Unlike the LVQ algorithm, this algorithm minimizes the network output errors which are the differences of clas s membership target and actual membership values, and results to minimize the distances between training patterns and competing neurons. Speaker Adaptation in speech synthesis is performed as follow;input speaker's codebook is mapped a reference speaker's codebook in fuzzy concepts. The Fuzzy VQ mapping replaces a codevector preserving its fuzzy membership function. The codevector correspondence histogram is obtained by accumulating the vector correspondence along the DTW optimal path. We use the Fuzzy VQ mapping to design a mapped codebook. The mapped codebook is defined as a linear combination of reference speaker's vectors using each fuzzy histogram as a weighting function with membership values. In adaptive-speech synthesis stage, input speech is fuzzy vector-quantized by the mapped codcbook, and then FCM arithmetic is used to synthesize speech adapted to input speaker. The speaker adaption experiments are carried out using speech of males in their thirties as input speaker's speech, and a female in her twenties as reference speaker's speech. Speeches used in experiments are sentences /anyoung hasim nika/ and /good morning/. As a results of experiments, we obtained a synthesized speech adapted to input speaker.

• The Transactions of the Korea Information Processing Society
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• v.7 no.2
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• pp.520-528
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• 2000

he speed of microprocessor getting faster, the data transfer width between the microprocessor and the memory becomes a critical part to limit the system performance. So the study of the computer architecture with the high code density is cmerged. In this paper, a tentative Bi-Length Instruction Set Computer(BISC) that consists of 16 bit and 32 bit length instructions is proposed as the high code density 32 bit microprocessor architecture. The 32 bit BISC has 16 general purpose registers and two kinds of instructions due to the length of offset and the size of immediate operand. The proposed 32 bit BISC is implemented by FPGA, and all of its functions are tested and verified at 1.8432MHz. And the cross assembler, the cross C/C++ compiler and the instruction simulator of the 32 bit BISC are designed and verified. This paper also proves that the code density of 32 bit BISC is much higher than the one of traditional architecture, it accounts for 130~220% of RISC and 130~140% of CISC. As a consequence, the BISC is suitable for the next generation computer architecture because it needs less data transfer width. And its small memory requirement offers that it could be useful for the embedded microprocessor.

• Journal of Korea Multimedia Society
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• v.3 no.2
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• pp.192-200
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• 2000

8 bit and 16 bit microprocessors are widely used in the small sited control machine. The embedded microprocessors which is integrated on a single chip with the memory and I/O circuit must have simple hardware circuit and high code density. This paper proposes a 16 bit high code density EISC(Extendable Instruction Set Computer) microprocessor. SE1608 has 8 general purpose registers and 16 bit fixed length instruction set which has the short length offset and small immediate operand. By using an extend register and extend flag, the offset and immediate operand in instruction could be extended. SE1608 is implemented with 12,000 gate FPGA and all of its functions have been tested and verified at 8MHz. And the cross assembler, the cross C/C++compiler and the instruction simulator of the SE1608 have been designed and verified. This paper also proves that the code density$.$ of SE1608 shows 140% and 115% higher code density than 16 bit microprocessor H-8300 and MN10200 respectively, which is much higher than traditional microprocessors. As a consequence, the SE1608 is suitable for the embedded microprocessor since it requires less program memory to any other ones, and simple hardware circuit.

• Transactions of the Korean Society of Mechanical Engineers
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• v.16 no.10
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• pp.1915-1927
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• 1992

A three-dimensional Navier-Stokes code has been developed for analysis of viscous flows through turbomachinery blade rows or other internal passages. The Navier-Stokes equations are written in a cartesian coordinate system, then mapped to a general body-fitted coordinate system. Streamwise viscous terms are neglected and turbulent effects are modeled using the baldwin-Lomax model. Equations are discretized using finite difference method on the stacked C-type grids and solved using LU-ADI decomposition scheme. calculations are made for a two-dimensional cascade in a transonic wind-tunnel to see the infuence of the endwalls. The flow pattern of the three-dimensional flow near the endwall is found to be different from that of the two-dimensional flow due to the existence of the endwalls.

• Journal of KIISE:Computing Practices and Letters
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• v.5 no.4
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• pp.416-425
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• 1999

복잡한 무결성 제약 조건을 효율적으로 확인하기 위해 제약 조건들을 룰 베이스(rule base)에 저장하고 별도의 룰 관리 시스템과 제약 조건 관리 시스템을 통해 제약 조건을 확인하는 기법이 많은 연구자들에 의해 연구되고 발표되었다. 그러나 제약 조건 관리 시스템이 실행시간에 응용 프로그램을 항상 모니터링하고 있다가 데이타의 수정이 요청될 때마다 개입하여 프로세스를 중단시키고 관련 제약 조건을 확인하는 기존의 방법들은 처리 시간의 지연을 피할 수 없다. 본 논문은 컴파일 시간에 제약 조건 확인 코드를 응용 프로그램에 미리 삽입할 것을 제안한다. 응용 프로그램 자체 내에 제약 조건 확인 코드가 삽입되기 때문에 실행 시간에 다른 시스템의 제어를 받지 않고 직접 제약 조건의 확인 및 데이타베이스의 접근이 가능해져서 처리 시간의 지연을 피할 수 있을 것이다. 이를 위해 어떤 구문이 제약 조건의 확인을 유발하는 지를 추적하였고, 컴파일러가 그러한 구문을 어떻게 전처리 과정에서 검색하는지 그리고 그러한 구문마다 어떻게 해당 제약 조건 확인 코드를 삽입할 수 있는 지를 객체지향1) 데이타베이스 언어인 Objectivity/C++에 대해 gcc의 YACC 코드를 변경함으로써 보여 주었다.Abstract To cope with the complexity of handling integrity constraints, numerous researchers have suggested to use a rule-based system, where integrity constraints are expressed as rules and stored in a rule base. A rule manager and an integrity constraint manager cooperate to check the integrity constraints efficiently. In this approach, however, the integrity constraint manager has to monitor the activity of an application program constantly to catch any database operation. For each database operation, it has to check relevant rules with the help of the rule manager, resulting in considerable delays in database access. We propose to insert the constraints checking code in the application program directly at compile time. With constraints checking code inserted, the application program can check integrity constraints by itself without the intervention of the integrity constraint manager. We investigate what kind of statements require the checking of constraints, show how the compiler can detect those statements, and show how constraints checking code can be inserted into the program, by modifying the GCC YACC file for Objectivity/C++, an object-oriented database programming language.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.4
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• pp.285-292
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• 2007

SoC which deploys software modules as well as hardware IPs on a single chip is a major revolution taking place in the implementation of a system design, and high-level synthesis is an important process of SoC design methodology. Recently, SPARK parallelizing high-level synthesis software tool has been developed. It takes a behavioral ANSI-C code as an input, schedules it using code motion and various code transformations, and then finally generates synthesizable RTL VHDL code. Although SPARK employs various loop transformation algorithms, the synthesis results generated by SPARK are not acceptable for basic signal and image processing algorithms with nested loop. In this paper we propose a SoC platform with an application-specific PLD targeting local operations which are feature of many loop algorithms used in signal and image processing, and demonstrate design process which maps behavioral specification with nested loops written in a high-level language (ANSI-C) onto 2D systolic array. Finally the derived systolic array is implemented on the proposed application-specific PLD of SoC platform.

• Journal of the Korea Society of Computer and Information
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• v.7 no.4
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• pp.108-114
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• 2002

After automatic translation system for hangul's romanization based on the World Wide Web converting korean-word, sentence, document to Transliteration letters by applying algorithm based phonological principles. even though a user do not know the basic principles of the usage of Korean-to-Romanization notations, It refers to corresponding character table that has been currently adopted the authority's standard proposition for Korean-to-Romanization notation rule concurrently, add to make possible to convert a machinized code as well. It provides font for toggling Korean-English mode, insert-edit mode by assigning ASCII codes and Unicode are hardly used to them. This program could be made in C++ progamming language and Unified Modeling Language to implement various font. font-expanding and condensing. alternative printing.

• Proceedings of the Korea Information Processing Society Conference
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• 2006.05a
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• pp.447-450
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• 2006

본 논문에서는 C++ 컴파일러 구현과정에서 객체지향 언어의 속성을 처리하기 위한 역번역기(detranslator)를 설계하고 구현하였다. 구현된 역번역기는 C++ 컴파일러의 선언부 처리 과정에서 심벌 테이블에 입력된 속성들을 본래의 C++ 프로그램으로 역번역 한다. 따라서 C++ 컴파일러 개발 과정에서 설계된 심벌 테이블과 심벌테이블에 입력된 정보가 올바른지 쉽게 검증할 수 있다. 심벌 테이블은 C++ 컴파일러의 어휘 분석과 구문 분석 과정에서 인식되는 명칭(identifier)에 대하여 그 속성(attribute)들을 수집하여 저장하는 자료구조로, 심벌 테이블에 저장된 속성들은 의미분석(semantic analysis) 단계에서 참조된 명칭의 사용이 타당한지 검사하는데 사용 되어 코드 생성(code generation) 단계에서 올바른 코드가 생성 되도록 한다. 본 역번역기를 구현함으로써 심벌 테이블이 올바르게 설계 되었는지 검증할 수 있으며, 컴파일 할 때 심벌 테이블에 필요한 모든 속성이 저장되어 있는지 쉽게 확인 할 수 있게 되었다. 그리고 디버그 정보도 함께 출력되어 객체지향 언어를 위한 컴파일러 개발의 정확성을 기할 수 있다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.2C
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• pp.175-183
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• 2006

This letter proposes a Direct Sequence Spread Spectrum (DS-SS)-based Flight Termination System(FTS) and show the simulation results and implements the system using FRGAs. The DS-SS FTS has immunity interference signals and the influence of jamming signal. Moreover, a DS-SS FTS can provides effects on an authentication and encryption with spread codes. And the system uses more less power than an analog FM system. We used Reed-Solomon (32, 28) code and triple Data Encryption Standard(3DES) for error correction and data encryption. Also we used counter algorithm for unauthenticated device's attack The spread codes of In-phase channel and Quadrature channel were generated by Gold sequence generators. The system was implemented in Altera APEX20K100E FPGA for the ground system and EPF10K100ARC240-3 for the airborne system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.2
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• pp.199-208
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• 2014

Code division multiple access (CDMA) is one of the promising medium access control (MAC) schemes for underwater acoustic sensor networks because of its robustness against frequency-selective fading and high frequency-reuse efficiency. As a way of performance evaluation, sea or lake experiment has been employed along with computer simulation.. In this study, we design the underwater CDMA forward-link transceiver and evaluate the feasibility aginst harsh underwater acoustic channel in water-tank first. Then, based on the water-tank experiment results, we improved the transceiver and showed the improvements in a lake experiment. A pseudo random noise code acquisition process is added for phase error correction before decoding the user data by means of a Walsh code in the receiver. Interleaving and convolutional channel coding scheme are also used for performance improvement. Experimental results show that the multiplexed data is recovered by means of demultiplexing at receivers with error-free in case of two users while with less than 15% bit error rate in case of three and four users.