• KSCE Journal of Civil and Environmental Engineering Research
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• v.40 no.6
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• pp.603-611
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• 2020

This study collected and analyzed transportation card data in order to better understand the operation and usage of city buses in Ulsan Metropolitan City in Korea. The analysis used quantitative and qualitative indicators according to the characteristics of the data, and also the categories were classified as general status, operational status, and satisfaction. The existing city bus survey method has limitations in terms of survey scale and in the survey process itself, which incurs various types of errors as well as requiring a lot of time and money to conduct. In particular, the bus means indicators calculated using transportation card data were analyzed to compensate for the shortcomings of the existing operational status survey methods that rely entirely on site surveys. The city bus index calculated by using the transportation card data involves quantitative operation status data related to the user, and this results in the advantage of being able to conduct a complete survey without any data loss in the data collection process. We took the transportation card data from the entire city bus network of Ulsan Metropolitan City on Wednesday April 3, 2019. The data included information about passenger numbers/types, bus types, bus stops, branches, bus operators, transfer information, and so on. From the data analysis, it was found that a total of 234,477 people used the city bus on the one day, of whom 88.6% were adults and 11.4% were students. In addition, the stop with the most passengers boarding and alighting was Industrial Tower (10,861 people), A total of 20,909 passengers got on and off during the peak evening period of 5 PM to 7 PM, and 13,903 passengers got on and off the No. 401 bus route. In addition, the top 26 routes in terms of the highest number of passengers occupied 50% of the total passengers, and the top five bus companies carried more than 70% of passengers, while 62.46% of the total routes carried less than 500 passengers per day. Overall, it can be said that this study has great significance in that it confirmed the possibility of replacing the existing survey method by analyzing city bus use by using transportation card data for Ulsan Metropolitan City. However, due to limitations in the collection of available data, analysis was performed only on one matched data, attempts to analyze time series data were not made, and the scope of analysis was limited because of not considering a methodology for efficiently analyzing large amounts of real-time data.

• The KIPS Transactions:PartA
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• v.12A no.6 s.96
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• pp.523-530
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• 2005

When a PCI 2.2 bus master requests data using Memory Read command, a target device may hold PCI bus without data to be transferred for long time because a target device needs time to prepare data infernally. Because the usage efficiency of the PCI bus and the data transfer efficiency are decreased due to this situation, the PCI specification recommends to use the Delayed Transaction mechanism to improve the system performance. But the mechanism cann't fully improve performance because a target device doesn't know the exact size of prefetched data. In the previous work, we propose a new method called Prefetch Request when a bus master intends to read data from the target device. In this paper, we design PCI 2.2 controller and local device that support the proposed method. The designed PCI 2.2 controller has simple local interface and it is used to convert the PCI protocol into the local protocol. So the typical users, who don't know the PCI protocol, can easily design the PCI target device using the proposed PCI controller. We propose the basic behavioral verification, hardware design verification, and random test verification to verify the designed hardware. We also build the test bench and define assembler instructions. And we propose random testing environment, which consist of reference model, random generator ,and compare engine, to efficiently verify corner case. This verification environment is excellent to find error which is not detected by general test vector. Also, the simulation under the proposed test environment shows that the proposed method has the higher data transfer efficiency than the Delayed Transaction about $9\%$.

• Journal of Information Processing Systems
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• v.13 no.1
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• pp.95-103
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• 2017

The PCI Express is a widely used system bus technology that connects the processor and the peripheral I/O devices. The PCI Express is nowadays regarded as a de facto standard in system area interconnection network. It has good characteristics in terms of high-speed, low power. In addition, PCI Express is becoming popular interconnection network technology as like Gigabit Ethernet, InfiniBand, and Myrinet which are extensively used in high-performance computing. In this paper, we designed and implemented a evaluation platform for interconnect network using PCI Express between two computing nodes. We make use of the non-transparent bridge (NTB) technology of PCI Express in order to isolate between the two subsystems. We constructed a testbed system and evaluated the performance on the testbed.

• Proceedings of the KIEE Conference
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• 2001.04a
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• pp.349-352
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• 2001

FACTS technology is developed into the sophisticated system technology which combines conventional power system technology with power electronics, micro-process control, and information technology. Its objectives are achieving enhancement of the power system flexibility and maximum utilization of the power transfer capability through improvements of the system reliability, controllability, and efficiency [1]. As a series and shunt compensator, UPFC consists of two inverters with common dc link capacitor bank. It controls the magnitude of shunt bus voltage and real and reactive power flow of transmission line[2]. In this paper, we present the design, implementation and test results of developed 20kVA level prototype UPFC. It is applied to power system simulator and controls the real and reactive power flow and shunt bus voltage magnitude.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.10 no.1
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• pp.14-26
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• 2011

In this paper, we've studied Optical Fiber Subscribe Transmit system. After receiving the ATM cell passing through the FIFO of the Asynchronous Transfer Method from the ATM Layer images to the VC4 signal payload passing through scrambling of the cell payload, HEC computation of the cell and inserting the Idle/Unassigned cell. At this time formed VC4 signal passing through the generating and inserting POH overhead at the same time indicating the start point of the cell by the H4 byte on the VC4 POH. This ATM cell transmits 155Mbps speed changing the optical signal after outputting the frame format at the STM-1 signal generation block through the AUG bus after generating J1 of the VC4 start point at the AU4 pointer generation block.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.302-312
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• 2001

As the data transfer rate between chips gets higher, both crosstalk and SSN (Simultaneous Switching Noise) deteriorate seriously the performance of a system. The proposed interface scheme uses P-CTR and N-CTR(Positive/Negative Constant Transition Rate) which encodes data at both falling and rising edges, where the transition directions of N-CTR and P-CTR are opposite. And the proposed bus system places two P-CTR drivers and two N-CTR drivers alternatively. In the proposed P/N-CTR interface scheme, the signals of neighboring interconnection lines at both sides of a bus will not switch simultaneously in the same direction, which leads to reduction in the maximum crosstalk and SSN compared to conventional interfaces. For verification of noise reduction of the proposed interface scheme, the scheme is applied to several kinds of bit-wide buses with various interconnection structures, and HSPICE simulation was performed with 0.35 ${\mu}{\textrm}{m}$ SPICE parameters. The simulation results show that in the 32-bit or less wide bus, the maximum SSN and crosstalk are reduced to at least 26.78% and 50%, respectively in comparison with the conventional interface scheme.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.959-962
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• 2003

At the processing capabilities and operating frequency of embedded system are growing, so is the needed data bandwidth to fully utilize the processing capability. The ability to transfer huge amount of data between the embedded core and external devices is required for efficient system operation. In this paper, the data communication architecture for the mixed-clock system is proposed. The dynamic priority adaptation algorithm for bus arbitration is proposed for bandwidth guarantee. The communication architecture that incorporates the proposed arbitration algorithm adapts the priority of communication components dynamically based on the information from FIFO. The experiments show that the measured bandwidth of each component traces the required bandwidth well compared to the other arbitration algorithms

• Information and Communications Magazine
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• v.25 no.12
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• pp.10-18
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• 2008

In this paper, we present a low-power design of H.264 codec based on dedicated hardware and software solution on EMP(ETRI Multi-core platform). The dedicated hardware scheme has reducing computation using motion estimation skip and reducing memory access for motion estimation. The design reduces data transfer load to 66% compared to conventional method. The gate count of H.264 encoder and the performance is about 455k and 43Mhz@30fps with D1(720x480) for H.264 encoder. The software solution is with ASIP(Application Specific Instruction Processor) that it is SIMD(Single Instruction Multiple Data), Dual Issue VLIW(Very Long Instruction Word) core, specified register file for SIMD, internal memory and data memory access for memory controller, 6 step pipeline, and 32 bits bus width. Performance and gate count is 400MHz@30fps with CIF(Common Intermediated format) and about 100k per core for H.264 decoder.

• Proceedings of the Korea Information Processing Society Conference
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• 2020.11a
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• pp.526-527
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• 2020

본 연구는 대중교통 활용도를 높이고자 효율적인 버스 환승지 추천 서비스를 설계한다. 제주데이터 허브에서 입수한 승하차데이터를 처리하여 승객수와 버스의 정류장 도착시간 등을 예측함은 물론 인터넷 연결을 통해 버스정보시스템과 연동하여 현재의 교통상황을 실시간으로 입수하여 효율적인 환승지를 추천한다. 승객은 변동되는 교통상황에 따라 이동중에도 더 좋은 환승 노선으로 변경할 수 있으며 데이터센터 관점에서는 축적되고 있는 버스 데이터의 활용도도 높일 수 있다.

• Journal of the Economic Geographical Society of Korea
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• v.10 no.1
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• pp.44-63
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• 2007

The purpose of this study is to propose mining processes in the large trip-transaction database of the Metropolitan Seoul area and to analyze the spatial characteristics of travel behavior. For the purpose. this study introduces a mining algorithm developed for exploring trip patterns from the large trip-transaction database produced every day by transit users in the Metropolitan Seoul area. The algorithm computes trip chains of transit users by using the bus routes and a graph of the subway stops in the Seoul subway network. We explore the transfer frequency of the transit users in their trip chains in a day transaction database of three different years. We find the number of transit users who transfer to other bus or subway is increasing yearly. From the trip chains of the large trip-transaction database, trip patterns are mined to analyze how transit users travel in the public transportation system. The mining algorithm is a kind of level-wise approaches to find frequent trip patterns. The resulting frequent patterns are illustrated to show top-ranked subway stations and bus stops in their supports. From the outputs, we explore the travel patterns of three different time zones in a day. We obtain sufficient differences in the spatial structures in the travel patterns of origin and destination depending on time zones. In order to examine the changes in the travel patterns along time, we apply the algorithm to one day data per year since 2004. The results are visualized by utilizing GIS, and then the spatial characteristics of travel patterns are analyzed. The spatial distribution of trip origins and destinations shows the sharp distinction among time zones.