• Journal of the Korean Operations Research and Management Science Society
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• v.19 no.3
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• pp.1-14
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• 1994

In this paper, an analytical model of the message delay in the DQDB (Distributed Queue Dual Bus) network is investigated. The DQDB network has been adopted as a subnetwork for the IEEE 802 MAN (Metropolitan Area Network) standard. The DQDB network consists of two high speed undirectional buses and a series of stations attached to both of the buses. Massages arriving at each station consists of severla packets according to its size. This system is approximated into " $B^{[x]}$/G/1 with exceptional first service queueing " by defining the concept of service time on a packet. The service time for a packet is defined as the time from the instant the packet arrives at the transmission buffer until the time the packet is fully transmitted. By using the BASTA property and the average work in the system, the mean message delay time is obtained.age work in the system, the mean message delay time is obtained.d.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.7
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• pp.1177-1182
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• 2007

Recently, IEC61850 supports the standardized communication technique in both station bus and process bus, and presents the substation automation model. In this paper, we propose the required techniques to develop the Merging Unit (MU), which is one of the important data acquisition equipment in substation automation, under IEC61850 communication protocol. Especially, we also propose the precision time synchronization technique using GPS(Global Positioning System) for the MU. IEC61850-9-2 SV (Sampled Value) service is applied to the MU which is designed using microprocessor. In order to evaluate the performance of the proposed MU, the playback program, which can reconstruct the transmitted sampled value data on the basis of time information, is developed and the performance of the IEC61850 SV service for MU is verified experimentally.

• Journal of Institute of Control, Robotics and Systems
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• v.5 no.5
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• pp.600-613
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• 1999

This paper focuses on development of a performance manager for IEEE 802.4 token bus networks to serve large-scale integrated systems. In order to construct the management algorithm, the principles of fuzzy logic, genetic algorithm, and neural network have been combined to represent human knowledge and to imitate of human inference mechanism. Through the simulation experiments, it is shown that the proposed performance manager is capable of improving the network performance without a priori knowledge.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.10
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• pp.720-726
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• 2004

The data transmission over MVB(Multifunction Vehicle Bus) of TCN(Train Communication Network) is divided into the periodic transmission phase and the sporadic transmission phase. TCN standard recommends the event-polling method as the message transfer in the sporadic phase. However, since the event-polling method does not use pre-scheduling to the priority of the messages, it is inefficient for the real-time systems. To schedule message transmission, a master node should know the priority of message to be transmitted by a slave node prior to the sporadic phase, but the existing TCN standard does not support any protocol for this. This paper proposes the slave frame bit-stuffing algorithm, with which a master node gets the necessary information for scheduling and includes the simulation results of the event-polling method and the proposed algorithm.

• Proceedings of the KIEE Conference
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• 2006.04a
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• pp.195-197
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• 2006

In this paper, an interface unit is designed to efficiently monitor transmission data in Controller Area Network(CAN)-based control systems. The CAN uses a serial multi master communication protocol that efficiently supports distributed real-time control with a very high level of data integrity, and communication speeds of up to 1Mbps. The interface unit is composed of a DSP controller which collects data on the CAN bus and transfers data to a personal computer via serial communication to save and display of interesting signals. The experimental system consists of three DSP controllers which represent electronic control units of a vehicle, an interface unit for analysing the data on the bus, and a graphic monitoring program coded on the Windows platform. The validity and the effectiveness of the proposed simple type of CAN interface unit are shown through the experimental results.

• Journal of the Korean Society for Precision Engineering
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• v.13 no.6
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• pp.152-160
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• 1996

This paper focuses on development and evaluation of a performance management algorithm for IEEE 802.4 token bus networks to serve large-scale integrated manufacturing systems. Such factory automation networks have to satisfy delay constraints imposed on time-critical messages while maintaining as much network capacity as possible for non-time-critical messages. This paper presents a network performance manager that adjusts queue capacity as well as timers by using a set of fuzzy rules and fuzzy inference mechanism. The efficacy of the performance management has been demonstrated by a series of simulation experiments.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.287-290
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• 2002

This paper rotates to tile FPGA that is reffered to as the UTOSPI. The design goal of the FPGA is to convert the UTOPIA-3 bus interface to the SPI-3 bus interface, so that the SAR chips on the ATM interface board can be interfaced to the packet processor through this FPGA. We Propose a new architecture that has two Dual Port RAMs and flow control signals. To buffer data, the UTOSPI has a Dual port RAM in the receive direction and the same size of that in the transmit direction. This design has been implemented, compiled, and tested using a Xilinx Virtex-I XCV-300E FPGA.

• Journal of IKEEE
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• v.20 no.3
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• pp.333-336
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• 2016

LIN (local interconnect network) is a standard low-speed serial communication protocol, and it was developed as an efficient sub-bus for automotive electronic modules. In this paper, a LIN controller was implemented in Verilog HDL, based on LIN ver. 2.2A. The implemented LIN controller was verified in FPGA, and it can be supplied as an IP to be integrated into SoC system. Its size is about 2,300 gates when synthesized in 0.18um technology.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.959-961
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• 2003

In this paper, we describe implemented DMAC (Direct Memory Access Controller) architecture on Altera's $Excalibur^{TM}$ that includes industry-standard $ARM922T^{TM}$ 32-bit RISC processor core operating at 200 MHz. We implemented DMAC based on AMBA (Advanced Micro-controller Bus Architecture) AHB (Advanced Micro-performance Bus) interface. Implemented DMAC has 8-channel and can extend supportable channel count according to user application. We used round-robin method for priority selection. Implemented DMAC supports data transfer between Memory-to-Memory, Memory-to-Peripheral and Peripheral-to-Memory. The max transfer count is 1024 per a time and it can support byte, half-word and word transfer according to AHB protocol (HSIZE signals). We implemented with VHDL and functional verification using $ModelSim^{TM}$. Then, we synthesized using $LeonardoSpectrum^{TM}$ with Altera $Excalibur^{TM}$ library. We did FPGA P&R and targeting using $Quartus^{TM}$. We can use implemented DMAC module at any system that needs high speed and broad bandwidth data transfers.

• Proceedings of the Korea Information Processing Society Conference
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• 2000.04a
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• pp.149-154
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• 2000

시스템이 복잡해짐에 따라 현재 사용되고 있는 무작위적 테스트나 시뮬레이션은 프로토콜의 정확성을 확인하기에 충분하지 못하므로 보다 효율적이고 믿을 만한 검증 방법이 필요하다. 본 논문은 ETRI에서 개발한 디렉토리 기반 CC-NUMA시스템의 CCA(Cache Coherent Agent)보드 내부 버스인 I-Link(Inside Link) 버스의 중재 프로토콜을 정형 검증에 쓰이는 도구 중의 하나인 VIS(Verification Interacting with Synthesis)를 이용하여 검증한다. VIS는 Verilog 입력을 받는 도구이므로 개발 단계에서 만들어진 소스를 그대로 이용하여 검증하는 기법을 사용하였고 이를 통해 보다 정확한 명세와 검증을 할 수 있었다.