• ETRI Journal
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• v.10 no.3
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• pp.83-91
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• 1988

This paper describes the architecture and the performance analysis of a multiprocessor system, which is based on the shared memory and single system bus. The system bus provides the pended protocol for the multiprocessor environment. Analyzing the processor utilization, address/data bus utilization and memory conflicts, we use a simulation model. The hit ratio of private cache memory is a major factor on the linear increase of the performance of a shared memory based multiprocessor system.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.41 no.2
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• pp.107-117
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• 1992

This paper presents an improved algorithm of optimal measurement design with a reliability evaluation method for a large power system. The proposed algorithm is developed to consider the dummy bus and to achieve highest accuracy of the state estimator as well with the limited investment cost. The dummy bus in the power system is impossible to install measurement meter, while real and reactive power measurements is considered in the proposed algorithm. On the other hand, P/C model is developed by taking advantage of the matrix sparsity. The improved program is successfully tested for KEPCO system with PSS/E lineflow calculated data package.

• Proceedings of the KIEE Conference
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• 1999.07c
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• pp.1054-1056
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• 1999

It is the most important in small signal stability analysis of large scale Power systems to compute only the dominant eigenvalues selectively with numerical stability and efficiency. In this Paper evoluted linear analysis program, transformed state matrix using Inverse transformation with complex shift and then Hessenberg process and iterative scheme are used to accelerate Hessenberg process, can calculate dominant eigenvalues. In this Paper, The accuracy of this Program has been validated against 4-machines 11-bus system and New England 10-machines 39-bus system. Also applied to KEPCO system - about 791-bus 250-machines 2500-branches, got 2568 order state matrix, and calculated two dominant modes. This analysis result equaled to result of EPRI's SSSP program to use commonly, and calculating time is faster.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.7
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• pp.446-452
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• 2020

As the use of children's school buses increases, accidents caused by the negligence of school bus drivers and ride carers have also increased significantly. To prevent such accidents, the government is coming up with various policies. We propose an accident prevention and safety management system for children's school buses. Through this system, bus drivers can easily check whether each child is seated and whether the seat belt is used, so it is possible to quickly respond to children's conditions while driving. With the ability to recognize faces by analyzing camera images, children can use a seat belt that is automatically adjusted to their height. It is therefore possible to prevent secondary injuries that may occur in the event of a traffic accident. In addition, a sleeping child-check system is provided to confirm that all children get off the bus, and a text service is provided to inform parents of their children's locations in real time. Based on Raspberry Pi, the system is implemented with cameras, pressure sensors, motors, Bluetooth modules, and so on. This proposed system was attached to a bus model to confirm that the series of functions work correctly.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.745-753
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• 2016

This paper presents a fully synthesizable low power interconnect bus for millimeter-scale wireless sensor nodes. A segmented ring bus topology minimizes the required chip real estate with low input/output pad count for ultra-small form factors. By avoiding the conventional open drain-based solution, the bus can be fully synthesizable. Low power is achieved by obviating a need for local oscillators in member nodes. Also, aggressive power gating allows low-power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with a power management unit that has nW standby mode. A 3-module system including the bus is fabricated in a 180 nm process. The entire system consumes 8 nW in standby mode, and the bus achieves 17.5 pJ/bit/chip.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.4
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• pp.148-159
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• 2005

We propose a technique for finding the worst case response time (WCRT) of a DMA request that is needed in the schedulability analysis of a whole real-time system. The technique consists of three steps. In the first step, we find the worst case bus usage pattern of each CPU task. Then in the second step, we combine the worst case bus usage pattern of CPU tasks to construct the worst case bus usage pattern of the CPU. This second step considers not only the bus requests made by CPU tasks individually but also those due to preemptions among the CPU tasks. finally, in the third step, we use the worst case bus usage pattern of the CPU to derive the WCRT of DMA requests assuming the fixed-priority bus arbitration protocol. Experimental results show that overestimation of the DMA response time by the proposed technique is within $20\%$ for most DMA request sizes and that the percentage overestimation decreases as the DMA request size increases.

• Archives of design research
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• v.16 no.4
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• pp.405-412
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• 2003

This research investigated the preference factor which has an effect on the forms of bus stop shelter in order to grasp the visual preference factor, which is necessary for planning and designing of bus stop shelter centering around user, starting with the question of the research regarding that a shelter is preferred by what kind of factor when the environmental conditions are regular. This research examined the relation between visual preference and preference factor which has an effect on it with Multiple Regression Analysis after evaluating visual preference for shelter form by user as applying of scoring system of Interval Scale. The result of the factor analysis by visual evaluation for the form of bus stop shelter through the said research result will have an great effect on the design of bus stop shelter centering around its user. Therefore, this research result will give a knowledge which is necessary for the plan and the installation of bus stop shelter, and contributes to shelter design and bus stop promotion which can maximize the satisfaction of user. As well, concerning the management of bus stop facilities, it will give useful guidelines for planning strategically the shelter management centering around user. In particular, It is estimated that the preference factor analysis by visual evaluation of the mass transportation user in daily life will be the cardinal point for bus stop plan.

• ETRI Journal
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• v.27 no.5
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• pp.497-503
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• 2005

In this paper, we present a performance analysis for an MPEG-4 video codec based on the on-chip network communication architecture. The existing on-chip buses of system-on-a-chip (SoC) have some limitation on data traffic bandwidth since a large number of silicon IPs share the bus. An on-chip network is introduced to solve the problem of on-chip buses, in which the concept of a computer network is applied to the communication architecture of SoC. We compared the performance of the MPEG-4 video codec based on the on-chip network and Advanced Micro-controller Bus Architecture (AMBA) on-chip bus. Experimental results show that the performance of the MPEG-4 video codec based on the on-chip network is improved over 50% compared to the design based on a multi-layer AMBA bus.

• Journal of Korean Society of Transportation
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• v.14 no.1
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• pp.69-80
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• 1996

In most cities, travel demand is distributed along long corridors and its destinations tend to concentrate in a central business district. For this kind of many-to-one or one-to-many travel demand pattern, a zonal operation of buses can be an efficient bus operation technique in which a long bus-demand corridor is divided into service zones and each service zone is provided with its own bus route connecting the service zone and single destination separately. This paper develops models of the total transportation costs for a single-zone operation and 2-zonal operation of buses for a long demand corridor with single destination in terms of various cost parameters, demand density, bus operation speeds, and location of the boundary between two service zones. In this study the total transportation cost is assumed to consist of the bus operation cost, passenger waiting cost and passenger travel time cost. It was proved that a zonal operation of buses can be more efficient than a single-zone operation for certain circumstances of the system and an boundary condition between two operation techniques was obtained. Also, several case studies were performed for various values of the cost parameters.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.2 s.105
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• pp.148-151
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• 2006

The DC power-bus' resonance is frequently attributed to EMI sources in the PCBs. Subsequently, it will ruin the digital signal integrity within one system or between adjacent systems in the form of conducted or radiated emission. Hence, since it is of importance to examine the PCB's emission, this paper sheds a light on the radiated emission from the power-bus with regards to its resonance modes. A full-wave analysis method is used to calculate the impedance and radiated electric fields and is validated by physics and an EM analysis tool.