• KSCE Journal of Civil and Environmental Engineering Research
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• v.38 no.1
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• pp.167-174
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• 2018

This study attempts to construct a model of optimal headway, focusing on a practical applicability to bus transit operation. Examining the existing bus operation and scheduling plans imposed by Busan City, we found that the plans failed to reasonably take into account such realities as varying traffic and operational conditions. The model is thus developed to derive the hourly optimal headway by routes satisfying the real-world conditions: varying hourly demand and cycle time, applying the model to routes 10 and 27 as examples. To do so, we collect big-dataset generated by smart card system and BIMS (Bus Inforamtion Management System). It is expected that the results of this study wil be a basis for further refined research in this field as well as for preparing practical timetables for bus operation.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.4
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• pp.148-159
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• 2005

We propose a technique for finding the worst case response time (WCRT) of a DMA request that is needed in the schedulability analysis of a whole real-time system. The technique consists of three steps. In the first step, we find the worst case bus usage pattern of each CPU task. Then in the second step, we combine the worst case bus usage pattern of CPU tasks to construct the worst case bus usage pattern of the CPU. This second step considers not only the bus requests made by CPU tasks individually but also those due to preemptions among the CPU tasks. finally, in the third step, we use the worst case bus usage pattern of the CPU to derive the WCRT of DMA requests assuming the fixed-priority bus arbitration protocol. Experimental results show that overestimation of the DMA response time by the proposed technique is within $20\%$ for most DMA request sizes and that the percentage overestimation decreases as the DMA request size increases.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.281-284
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• 2008

This paper describes ASIC design of multimedia SoC Platform. The implemented Platform consists of 32-bit OpenRISC1200 Microprocessor, WISHBONE on-chip bus, VGA Controller, Debug Interface, SRAM Interface and UART. The 32-bit OpenRISC1200 processor has 5 stage pipeline and Harvard architecture with separated instruction/data bus. The VGA Controller can display RCB data on a CRT or LCD monitor. The Debug Interface supports a debugging function for the Platform. The SRAM Interface supports 18-bit address bus and 32-bit data bus. The UART provides RS232 protocol, which supports serial communication function. The Platform is design and verified on a Xilinx VERTEX-4 XC4VLX80 FPGA board. Test code is generated by a cross compiler' and JTAG utility software and gdb are used to download the test code to the FPGA board through parallel cable. Finally, the Platform is implemented into a single ASIC chip using Chatered 0.18um process and it can operate at 100MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.8
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• pp.98-105
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• 2008

FlexRay is a high-speed communications protocol with high flexibility and reliability. It was devised by automotive manufacturers and semiconductor vendors and implemented as on vehicle LAN protocol using x-by-wire systems. FlexRay provides a high speed serial communication, time triggered bus and fault tolerant communication between electronic devices for automotive applications. In this paper, we first design the FlexRay communication controller, bus guardian protocol specification and function parts using SDL (Specification and Description Language). Then, the system is re-designed using Verilog HDL based on the SDL source. The FlexRay system was synthesized using Samsung $0.35{\mu}m$ technology. It is shown that the designed system can operate in the frequency range above 76 MHz. In addition, to show the validity of the designed FlexRay system, the FlexRay system is combined with automobile advance alarm system in vehicle applications. The FlexRay system is implemented using ALTERA Excalibur ARM EPXA4F672C3. It is shown that the implemented system operates successfully.

• Journal of the Korean Data and Information Science Society
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• v.26 no.5
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• pp.1061-1069
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• 2015

Recently, transportation big data generated in the transportation sector has been widely used in the transportation policies making and efficient system management. Bus passengers' mobility patterns are useful insight for transportation policy maker to optimize bus lines and time intervals in a city. We propose a new methodology to discover mobility patterns by using transportation card data. We first estimate the bus stations where the passengers get-off because the transportation card data don't have the get-off information in most cities. We then applies LDA (Latent Dirichlet Allocation), the most representative topic modeling technique, to discover mobility patterns of bus passengers in Cheong-Ju city. To understand discovered patterns, we construct a data warehouse and perform multi-dimensional analysis by bus-route, region, time-period, and the mobility patterns (get-on/get-off station). In the case of Cheong Ju, we discovered mobility pattern 1 from suburban area to Cheong-Ju terminal, mobility pattern 2 from residential area to commercial area, mobility pattern 3 from school areas to commercial area.

• Journal of Industrial Convergence
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• v.18 no.1
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• pp.25-33
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• 2020

South Korea entered an aged society phase in 2017 with the elderly accounting for 14% or higher of the entire population. It is expected to enter a super-aged society phase in 2026. The mobility handicapped, including the disabled and the elderly, are expected to grow continuously, and the demand for transport service for the mobility handicapped will definitely increase further. Thus, there is thus a need for various research to increase the utilization rate of low-floor buses among the mobility handicapped. This study analyzed the locations of getting on and off transportation means, time of departure and arrival, purpose of use, and frequency of use by the day among the mobility handicapped by making use of the information about their use of special transport service run by the mobility support center for the mobility handicapped. The study then proposed a method of selecting locations for low-floor bus stops to reflect the distribution and need of getting on and off transportation means among the mobility handicapped with such spatial analysis techniques as geocoding, overlapping analysis, buffer analysis, and generate tessellations. Finally, the study selected 228 locations for low-floor bus stops in Cheonan and reported a need to add 35 low-floor bus stops after eliminating the ones where the locations overlapped the old ones.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2633-2640
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• 2009

We design a small-area, low-power, and high-speed EEPROM for touch screen controller IC. As a small-area EEPROM design, a SSTC (side-wall selective transistor) cell is proposed, and high-voltage switching circuits repeated in the EEPROM core circuit are optimized. A digital data-bus sensing amplifier circuit is proposed as a low-power technology. For high speed, the distributed data-bus scheme is applied, and the driving voltage for both the EEPROM cell and the high-voltage switching circuits uses VDDP (=3.3V) which is higher than the logic voltage, VDD (=1.8V), using a dual power supply. The layout size of the designed 128-KBit EEPROMIP is $662.31{\mu}m{\times}1314.89{\mu}m$.

• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2914-2922
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• 1997

For FA (factory automation) and ATE (automatic test equipment) in the industrial area, the standard bus needs to increase the system performance of multiprocessor environment. VME(versa module european package format) bus is appropriated to the standard bus but has features of small package and low board density. Beside, the density of board and semiconductor have grown to become significant issues that affect development time, project cost and field diagnostics. To fit this trend, in this paper, we composed Revision C.1 (IEEE std. P1014-1987) of the integrated environment for the main function such as arbitration, interrupt and interface between, VMEbus and several control modules Also the designed, VME system controller is implemented on FPGA that can be located even into slot 1. The control and function modules are coded with VHDL mid-fixed description method and then those operations are verified by simulation. As a result of experiment, we confirmed the most important that is the operation of Bus timer about Bus error signal should occur within $56{\mu}m$, and both control and function modules have the reciprocal operation correctly. Thus, the constructed VHDL library will be able to apply the system based VMEbus and ASIC design.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.24-31
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• 2007

Up to date, a lot of bus protocol and bus architecture are released though most of them are based on the shared bus architecture and inherit the limitation of performance. SNP (SoC Network Protocol), and hence, SNA (SoC Network Architecture) which are high performance on-chip-bus protocol and architecture, respectively, have been proposed to solve the problems of the conventional shared bus. We refine the SNA specification and improve the performance and functionality. The performance of the SNA is improved by supporting simultaneous routing for bus request of multiple masters. The internal routing logic is also improved so that the gate count is decreased. The proposed SNA employs XSNP (extended SNP) that supports almost perfect compatibility with AMBA AHB protocol without performance degradation. The hardware complexity of the improved SNA is not increased much by optimizing the current routing logic. The improved SNA works for IPs with the original SNP at its best performance. In addition, it can also replace the AMBA AHB or interconnect matrix of a system, and it guarantees simultaneous multiple channels. That is, the existing AMBA system can show much improved performance by replacing the AHB or the interconnect matrix with the SNA. Thanks to the small number of interconnection wires, the SNA can be used for the off-chip bus system, too. We verify the performance and function of the proposed SNA and XSNP simulation and emulation.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.1
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• pp.47-52
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• 2017

This study is BIT(: Bus Information Terminal) features that take advantage of KEPCO eIoT(: energy Internet of Thing) platform, and it's Network configuration is composed of display terminal device, gateway, platform, and the service server. The key features are parts for processing protocol data between the gateway and the device using LoRa(: Long Range) technology, Intelligent applications and SIP(: Session Initiation Protocol) data handling connected to the Taxi reservation system. And the resource tree provided BIT for the service, which commonly used in the application server and the device.