• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.8
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• pp.951-957
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• 1999

The saddle node bifurcation (SNB) and the distance voltage instability are valuable information in power system planning and operation. This paper presents a new efficient, robust and unified strategy to compute the SNB by the combined use of the continuation power flow (CPF), Point of Collapse (PoC) method, and the method of a pair of multiple load flow solutions (PMLFS) with Lagrange interpolation utilizing only their advantages: the approximate nose curves and critical loading are determined fast by Lagrange-interpolating two stable and two unstable solutions obtained by using the robust CPF and PMLFS; the exact SNB is computed by the quadratically converging PoC method. The proposed method has been tested on Klos-Kerner 11-bus, New England 30-bus, IEEE 118-bus and KEPCO 791-bus systems. The method is found to be so efficient that computation time for determining the SNB of the KEPCO 791-bus system is 17.82 sec by a notebook PC with 300 MHz Pentium processor.

• Proceedings of the Korean Society of Computer Information Conference
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• 2017.01a
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• pp.87-88
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• 2017

오늘날 도시의 규모가 커지고 도시의 기능이 점점 복잡해진다. 또한, 도시에는 사람들이 많이 살고 있으며, 계속해서 도시로 사람들이 모이게 된다. 그러므로 도시에서의 삶은 서로 간에 점점 더 가까워지고 많은 부분에서 이웃 사람들과 연결되고 공간과 시간을 공유하게 된다. 특히, 사람들이 대중교통을 이용하면서 원하든 원치 않았든 많은 소리에 노출 되며, 그 소리에 대한 영향으로 서로 피해를 보기도 한다. 서울은 세계에서 가장 혼잡한 도시 중 하나이며, 이런 서울의 대중교통 중 마을버스는 좁은 골목길을 포함해 도로를 다니며 시민들의 공공의 이동을 담담하고 있다. 이 마을버스를 사용하는 사람들은 일반적으로 차량 내에서 좋은 승차감, 높은 공기질 및 적은 소음에서 이용하기를 원한다. 본 논문에서는 마을버스의 실내 소음에 대한 성가심도를 소음도 및 혼잡도에 관하여 분석한다. 그리고 이러한 상황별로 어떠한 경우에 성가심도가 높은지를 판단하고, 저감하는 방법을 마련하도록 하고자 한다. 분석결과 마을버스 내부 소음은 새 차와 오래된 차에서 큰 차이를 보이지 않았고, 성가심도 또한 도로 상황에 따른 소음의 정도에 민감한 반응을 보임을 확인하였다. 그래서 저감대안으로는 차량의 소음이 적게 발생 시키는 운전과, 차량의 정비 등을 제안하고자 한다.

• Journal of Korea Spatial Information System Society
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• v.8 no.2 s.17
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• pp.1-11
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• 2006

This paper addresses a GIS (Geographic Information System) based system in order to reduce the rate of public transportation accidents occurring in Iranian roads network. Over the years, the road accidents are a major issue throughout the world. Today, particular consideration is given to those technologies which can lead to diminish on the number of critical incidents. One of the main factors resulting in accidents and fatalities rates growth is the speed violation of buses in Iranian road network. The conventional speed controlling approach in Iran based on the Tachograph which records vehicle's speed, time, and stoppage in the mechanical processing has many problems. Hence, this research is intended to design and implement a GIS-based system to manage road accident of Bus transportation system using offline tracking system. This was accomplished using a GIS-based technique that encompasses three steps. The first step is developing a GIS-based accident system. The second step includes designing and applying a tracking system inside 90 buses for recording Bus information for speed controlling. Lastly, by using mentioned system in police center, the illegal drivers' punishment would be considered properly. Overall, this system has been successfully applied in this work. Therefore, the police and transportation office are able to control and make policy to diminish the number of accident. It is anticipated that online tracking system through the Web GIS would be utilized In this system in the near future.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.33-44
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• 2011

In this paper, we presents a hybrid on-chip bus architecture based on the AMBA 3.0 AXI protocol for MPSoC with high performance and low power. Among AXI channels, data channels with a lot of traffic are designed by crossbar-switch architecture for massively parallel processing. On the other hand, addressing and write-response channels having a few of traffic is handled by shared-bus architecture due to the overheads of (areas, interconnection wires and power consumption) reduction. In experiments, the comparisons are carried out in terms of time, space and power domains for the verification of proposed hybrid on-chip bus architecture. For $16{\times}16$ bus configuration, the hybrid on-chip bus architecture has almost similar performance in time domain with respect to crossbar on-chip bus architecture, as the masters's latency is differenced about 9% and the total execution time is only about 4%. Furthermore, the hybrid on-chip bus architecture is very effective on the overhead reduction, such as it reduced about 47% of areas, and about 52% of interconnection wires, as well as about 66% of dynamic power consumption. Thus, the presented hybrid on-chip bus architecture is shown to be very effective for the MPSoC interconnection design aiming at high performance and low power.

• Journal of Korean Society of Transportation
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• v.35 no.3
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• pp.234-246
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• 2017

The Seoul metropolitan government introduced the bus information systems, bus rapid transit to increase travel speed and punctuality but still suffer from insufficiency. This paper delivers a study verifying the external factors at near the bus stops. The dependent variable was set to the standard deviation of (1) travel time and (2) travel time to and from the bus stop in this study. The independent variables were set to (1) the number of routes, (2) traffic volume by bus type, (3) the number of bus bays, (4) the possibility of passing, (5) the distance to crosswalks and intersections, and (5) the presence of residential road. The results showed that the most significant factors included the link section speed, number of bus bay, distance to crosswalk, and the possibility of passing.

• Proceedings of the Korean Society of Computer Information Conference
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• 2012.01a
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• pp.219-222
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• 2012

본 논문에서는 스마트폰 앱에 기반한 버스정보시스템 구현에 대한 소개를 한다. 기본적으로 버스운전자용 앱(APP)에 의해서 버스의 위치가 파악되고 이를 3G망을 활용하여 전송된 서버에서 가공하여 버스 승객들에게 위치정보를 알리는 시스템이다. 기본적으로 버스정보시스템이 가지는 시스템적인 특징을 스마트폰을 기반으로 개발하고 저비용으로 개발하도록 하여 영세한 사업자들에게 활용되도록 하는데 목적이 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.105-116
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• 2008

Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, we propose an efficient test access mechanism that exploits an on/off-chip bus bridge for the Advanced High-performance Bus (AHB) and Peripheral Component Interconnect (PCI) bus. The test application time is considerably reduced by providing dedicated test stimuli input paths and response output paths, and by excluding the bus direction tumaround delays. Experimental results show that area overhead and testing times are considerably reduced in both functional and structural test modes. The proposed technique can be a lied to the other types of on/off-chip bus bridges.

• The KIPS Transactions:PartD
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• v.19D no.2
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• pp.127-132
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• 2012

In the Seoul metropolitan bus network, it may be necessary for a bus passenger to pick up a parcel, which has been purchased through e-commerce, at his or her convenient bus stop on the way to home or office. The flow-capturing location-allocation model can be applied to select pickup points for such bus stops so that they maximize the captured passenger flows, where each passenger flow represents an origin-destination (O-D) pair of a passenger trip. In this paper, we propose a fast heuristic algorithm to select pickup points using a large O-D matrix, which has been extracted from five million transportation card transactions. The experimental results demonstrate the bus stops chosen as pickup points in terms of passenger flow and capture ratio, and illustrate the spatial distribution of the top 20 pickup points on a map.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.54-60
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• 2008

The bus architecture consists of a master initiating a communication transaction, a slave responding to the transaction, a arbiter selecting a master, a bridge connecting buses and so on. Recently this is more complicated and developed toward multi-bus architecture. In this paper, several cases of multi-shared bus architecture are discussed and in order to decrease the bridge latency, the architecture introducing a memory selector is proposed. Finally, a LCD controller using DMA master is integrated in this bus architecture that is verified due to RTL simulation and FPGA board test. DMA, LCD line buffer and SDRAM controller are normally operated in the timing simulation using ModelSim tool, and the LCD image is confirmed in the real FPGA board containing LCD panel.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.745-753
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• 2016

This paper presents a fully synthesizable low power interconnect bus for millimeter-scale wireless sensor nodes. A segmented ring bus topology minimizes the required chip real estate with low input/output pad count for ultra-small form factors. By avoiding the conventional open drain-based solution, the bus can be fully synthesizable. Low power is achieved by obviating a need for local oscillators in member nodes. Also, aggressive power gating allows low-power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with a power management unit that has nW standby mode. A 3-module system including the bus is fabricated in a 180 nm process. The entire system consumes 8 nW in standby mode, and the bus achieves 17.5 pJ/bit/chip.