• Journal of Power Electronics
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• v.18 no.5
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• pp.1595-1607
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• 2018

In this paper, a hierarchical control strategy is introduced to control a new three-port multidirectional DC-DC converter for integrating an energy storage system (ESS) to a bipolar DC microgrid (BPDCMG). The proposed converter provides a voltage-balancing function for the BPDCMG and adjusts the states of charge (SoC) of the ESS. Previous studies tend to balance the voltage of the BPDCMG buses with active sources or by transferring power from one bus to another. Furthermore, the batteries available in BPDCMGs were charged equally by both buses. However, this power sharing method does not guarantee efficient operation of the whole system. In order to achieve a higher efficiency and lower energy losses, a triple-layer hierarchical control strategy, including a primary droop controller, a secondary voltage restoration controller and a tertiary optimization controller are proposed. Thanks to the multi-functional operation of the proposed converter, its conversion stages are reduced. Furthermore, the efficiency and weight of the system are both improved. Therefore, this converter has a significant capability to be used in portable BPDCMGs such as electric DC ships. The converter modes are analyzed and small-signal models of the converter are extracted. Comprehensive simulation studies are carried out and a BPDCMG laboratory setup is implemented in order to validate the effectiveness of the proposed converter and its hierarchical control strategy. Simulation and experimental results show that using the proposed converter mitigates voltage imbalances. As a result, the system efficiency is improved by using the hierarchical optimal power flow control.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8C
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• pp.763-770
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• 2006

In this paper, a variable Reed-Solomon(RS) decoder with erasure decoding functionality is designed based on the modified Euclid's algorithm(MEA). The variability of the decoder is implemented through shortening and puncturing based on the RS(124, 108, 8) code, other than the primitive RS(255, 239, 8) code. This leads to shortening the decoding latency. The decoder performs 4-step pipelined operation, where each step is designed to be clocked by an independent clock. Thus by using a faster clock for the MEA block, the complexity and the decoding latency can be reduced. It can support both continuous- and burst-mode decoding. It has been designed in VHDL and synthesized in an FPGA chip, consuming 3,717 logic cells and 2,048-bit memories. The maximum decoding throughput is 33 MByte/sec.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8A
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• pp.820-829
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• 2006

IP-based design methodology has been popularly employed for SoC design to reduce design complexity and to cope with time-to-market pressure. Due to the request for high performance of current mobile systems, embedded SoC design needs a multi-processor to manage problems of high complexity and the data processing such as multimedia, DMB and image processing in real time. Interface module for communication between system buses and processors are required, since many IPs employ different protocols. High performance processors require interface module to minimize the latency of data transmission during read-write operation and to enhance the performance of a top level system. This paper proposes an automatic interface generation system based on FSM generated from the common protocol description sequence of a bus and an IP. The proposed interface does not use a buffer which stores data temporally causing the data transmission latency. Experimental results show that the area of the interface circuits generated by the proposed system is reduced by 48.5% on the average, when comparing to buffer-based interface circuits. Data transmission latency is reduced by 59.1% for single data transfer and by 13.3% for burst mode data transfer. By using the proposed system, it becomes possible to generate a high performance interface circuit automatically.