• 전자공학회논문지C
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• 제35C권8호
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• pp.10-22
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• 1998

To handle the density increase of SRAMs, a new parallel testing methodology based on built-in self test (BIST) is developed, which allows to access multiple cells simultaneously. The main idea is that a march algorithm is dperformed concurently in each baisc marching block hwich makes up whole memory cell array. The new parallel access method is very efficient in speed and reuqires a very thny hardware overhead for BIST circuitry. Results show that the fault coverage of the applied march algorithm can be achieved with a lower complexity order. This new paralle testing algorithm tests an .root.n *.root.n SRAM which consists of .root.k * .root.k basic marching blocks in O(5*.root.k*(.root.k+.root.k)) test sequence.

• 대한임베디드공학회논문지
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• 제5권4호
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• pp.217-224
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• 2010

Nowadays, people perform their tasks anywhere anytime using their mobile devices. For this reason, data synchronization (DS) between mobile devices and a central server has become one of the most essential technologies in mobile environments. Currently, several mobile DS protocols are proposed and used. However, the existing DS protocols cannot guarantee interoperability between them. To solve the problem, an embedded DS gateway has been developed in our previous study. The gateway runs on a Windows Mobile-based emulator. It converts data on a mobile device into common data specified by OMA DS standard protocol and vice versa. The embedded gateway has been built to support the OMA DS standard protocol. In order to verify that the embedded gateway conforms to the OMA DS standard protocol, two kinds of OMA conformance tests have to be conducted - interoperability test with an OMA DS-based server and conformance test with SCTS (SyncML Conformance Test Suit). In this paper, some parts of the gateway previously built are modified and the modified gateway is installed on a Windows Mobile-based smart phone. And the interoperability test and the conformance test with the SCTS are conducted. The results of the tests show that the embedded DS gateway operates properly on the Windows Mobile-based smart phone and that the gateway passes the tests, verifying its conformity to the OMA DS standard protocol. In addition, DS performance tests show that DS delay times between a real smart phone and a DS server increase gently as the number of DS data increases. In other words, the embedded DS gateway built in this paper can be used for a real smart phone at a reasonable performance cost.

• 한국농공학회지
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• 제44권7호
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• pp.36-45
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• 2002

Most of rural bridges have passed 30 years of age since they were built, which have to support unexpected overload caused by changed design load and excessive amount of transportation. For these rural bridges, repairs and replacements are needed. Even though there have been attempt to estimate the safety of existing bridges deteriorated with major defects, those approaches must rely on the observable damage and subsequent decisions are made subjectively. To avoid the high cost of rehabilitation, the bridge rating must correctly represent the present load-carrying capacity. Rating engineers use a methods such as Allowable Stress Design (ASD), Load Factor Design (LFD), and Load Resistance Factor Design (LRFD) to evaluate the bridge load carrying capacity. In this paper, the load rating methods are introduced, and it is illustrated how to use the load test data from literature survey. Load test is conducted to the bridge that was built 30 years ago in rural area. From load test results, new maintenance method is suggested instead of the bridge replacement.

• Steel and Composite Structures
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• 제26권3호
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• pp.315-328
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• 2018

Built-up Double-I (BD-I) columns consist of two hot rolled IPE sections and two cover plates which are welded by fillet welds. In Iran, this type of column is commonly used in braced frames with simple connections and sometimes in low-rise Moment Resisting Frames (MRF) with Welded Flange Plate (WFP) beam-column detailing. To evaluate the seismic performance of WFP connection of I-beam to BD-I column, traditional and modified exterior MRF connections were tested subjected to cyclic prescribed loading of AISC. Test results indicate that the traditional connection does not achieve the intended behavior while the modified connection can moderately meet the requirements of MRF connection. The numerical models of the connections were developed in ABAQUS finite element software and validated with the test results. For this purpose, moment-rotation curves and failure modes of the tested connections were compared with the simulation results. Moreover to avoid improper failure modes, some improvements of the connections were evaluated through a numerical study.

• 전자공학회논문지
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• 제52권6호
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• pp.70-76
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• 2015

본 논문은 FPGA 내부의 경계 스캔 체인을 자가 테스트 회로로써 재활용하기 위한 FPGA 자가 테스트 회로 설계 기술을 소개한다. FPGA의 경계 스캔 체인은 테스트나 디버깅 기능뿐만 아니라 각 셀에 연결되어 있는 입출력 핀의 기능을 설정하기 위해서도 사용되기 때문에 일반적인 칩의 경계 스캔 셀보다 매우 크다. 따라서, 본 논문에서는 FPGA 경계 스캔 셀의 구조를 분석하고 소수의 FPGA 로직과 함께 테스트 패턴 생성과 결과 분석이 가능하도록 설계한 BIST(built-in-self-test) 회로를 제시한다. FPGA의 경계 스캔 체인을 자가 테스트를 위하여 재사용함으로써 면적 오버헤드를 줄일 수 있고 보드상에서 프로세서를 사용한 온-라인(on-line) 테스트/모니터링도 가능하다. 실험을 통하여 오버헤드 증가량과 시뮬레이션 결과를 제시한다.

• 전력전자학회논문지
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• 제22권3호
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• pp.193-198
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• 2017

This paper discusses the design and control of a switched reluctance motor (SRM) drive system for a built-in car vacuum cleaner. The growing popularity of outdoor activities and recreation has led the automobile industry to expand technologies that increase the convenience of vehicles, and thus, a built-in car vacuum cleaner was introduced. However, the existing DC motor of a vacuum cleaning system has several disadvantages, such as maintenance cost and lifespan issues of its commutator-brush structure. An SRM can be a good alternative to the existing DC motor because of its high-speed capability, long lifespan, low maintenance cost, and high efficiency, among other advantages. A prototype SRM drive is designed and manufactured to verify its feasibility for use in a built-in car vacuum cleaning system. Dynamic simulation is conducted to determine the optimal switching angle for maximum efficiency and minimum torque ripple. Load test, noise measurement, and suction-power tests are also carried out.

• Steel and Composite Structures
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• 제18권6호
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• pp.1331-1351
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• 2015

Cold-formed built-up members are compression members that are common in multiple areas of steel construction, which include cold-formed steel joints and stud walls. These members are vulnerable to unique buckling behaviors; however, limited experimental research has been done in this area. Give this gap, experimental testing of 71 built-up members was conducted in this study. The variations of the test specimens include multiple lengths, intermediate welds, orientations, and thicknesses. The experimental testing was devised to observe the different buckling modes of the built-up C-channels and the effects of the geometrical properties; to check for applicability of multiple intermediate welding patterns; and to evaluate both the 2001 and 2007 editions of the American Iron and Steel Institute (AISI) Specification for built-up members in pure compression. The AISI-2001 and AISI-2007 were found to give inconsistent results that at times were un-conservative or overly conservative in terms of axial strength. It was also found that orientation of the member has an important impact on the maximum failure load on the member.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2012년도 한국컴퓨터종합학술대회논문집 Vol.39 No.1(B)
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• pp.214-216
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• 2012

BIT(Built-in Test)란 소프트웨어와 하드웨어의 기능 및 상태를 진단하고 오류에 대응하기 위한 방법론으로 빠른 오류 대처가 있어야 하는 다양한 분야에서 사용되고 있다. 현업에서의 BIT는 도메인의 특성에 따라 고려해야 하는 요소가 많으므로 각 도메인에 맞춰 구조화되지 않은 형태로 개발되고 있다. 따라서 기존 개발 방법론은 반복적인 작업이 수반되며 적용 환경 및 상활에 따라 변화하는 부분을 매번 새로 개발하기 위해 많은 인력과 시간이 필요하다는 문제점을 가진다. 이를 해결하기 위하여 본 논문에서는 개선된 BIT 개발 프로세스를 제안한다. 제안하는 프로세스는 BIT 처리 과정을 일반화하여 명세하고 이를 활용하여 BIT 처리 코트를 자동 생성한다. 그리고 BIT 코드를 검증할 수 있는 시뮬레이션 환경을 제공한다. 이를 통해 BIT 처리 구조 개발 과정의 편의성과 생산성을 향상하고 BIT 처리 구조의 유연성과 확장성 그리고 안정성을 높일 수 있다.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2012년도 춘계학술발표대회
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• pp.1208-1210
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• 2012

BIT(Built-In Test)란 S/W 또는 H/W 의 기능 및 상태를 진단하고 오류에 대응하기 위한 방법론으로 기능에 대한 신뢰성 및 빠른 오류 복구를 보장하기 때문에 다양한 분야에서 BIT 처리를 통해 시스템의 안정성을 높이고 있다. 현업에서의 BIT 는 도메인 특성에 따라 처리해야 하는 작업의 변화가 크기 때문에 구조화 되지 않은 형태로 각각 개발되고 있다. 따라서 BIT 개발 시 반복적인 작업이 수반되며 처리 과정의 수정 또는 처리 범위의 확장을 위해서는 많은 시간 및 인력이 요구된다. 이에 본 논문에서는 BIT 처리를 구조화하기 위하여 처리과정에 필요한 정보들을 일반화된 형태로 기록할 수 있도록 하는 BIT 처리 병세 방안과 BIT 처리 명세를 기반으로 한 자동 코드 생성 체계를 제안한다. 이를 통해 개발 과정의 편의성과 생산성을 향상하고 BIT 처리의 유연성과 확장성을 높일 수 있다.

• 항공우주시스템공학회지
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• 제13권3호
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• pp.48-55
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• 2019

본 논문은 무인항공기 체계(UAS; Unmanned Aerial Systems)의 고장이력관리장비(FHME; Fault History Management Equipment)에 관한 연구를 다룬다. 무인항공기 체계는 비행안전을 위하여 고신뢰성 설계를 기반으로 다양한 전자장비를 탑재하고 있으며, 이에 따른 신속한 고장탐지가 필요하여 각 탑재장비는 BIT(Built-In-Test) 기능을 보유한다. 이러한 BIT 정보를 지상에서 시현, 저장, 관리가 가능하도록 하기 위하여 고장이력관리장비를 개발하였다. 따라서 본 논문에서는 고장이력관리장비의 개요 및 개발 요구사항, 설계 결과, 검증 시험 결과에 대해 기술한다.