• 한국소음진동공학회:학술대회논문집
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• 한국소음진동공학회 2007년도 춘계학술대회논문집
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• pp.655-662
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• 2007

This paper presents a disk-type capacitive sensor for simultaneous measurement of five-dimensional motions of a target. The sensor can be manufactured with a printed circuit board (PCB) such that the sensor can be integrated with its electronics in a single PCB board, whereby the manufacturing costs is considerably reduced. The sensor is optimally designed through an error analysis of possible mechanical errors. Furthermore, the sensor can correct the horizontal motion measurement errors due to the sensor installation tilting error. A proto-type PCB sensor, electronics and a test rig were built, and the effectiveness of the developed sensor was proved through experiments.

• 정보처리학회논문지A
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• 제17A권2호
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• pp.103-112
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• 2010

클러스터 센서 네트워크는 여러 개의 중심 노드 주위에 다른 입력 노드들이 밀집된 분포를 보이는 센서 네트워크이다. 최소 스타이너 트리는 스타이너 포인트들을 도입하여 모든 입력 노드들을 최소 비용으로 연결하는 트리이다. 본 논문에서는 센서 노드와 베이스 스테이션의 연결인 간선들을, 클러스터 내에서와 클러스터 사이에서 각각 생성하고, 이를 이용하여 근사 최소 스타이너 트리를 반복적으로 생성하여, 단축된 길이의 클러스터 센서 네트워크를 구성하는 방법을 제안한다. 실행 시간 복잡도가 O($N^2$)인 제안된 방법으로 생성된 클러스터 센서 네트워크들은, 본 논문의 실험에서 유클리드 최소 신장 트리 방법의 네트워크들과 비교하여 생성 시간이 1170.5% 증가하였으나 최소치보다 0.1% 증가된 길이의 네트워크는 20.3%의 증가된 시간에 생성이 가능했다. 이 클러스터 센서 네트워크의 평균 길이는 유클리드 최소 신장 트리 방법과 비교하여 최대 3.7%, 평균 1.9% 감소되었다.

• 한국멀티미디어학회논문지
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• 제10권10호
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• pp.1260-1270
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• 2007

테스트 기술자들에게 아날로그 회로(또는 혼합신호 회로)의 테스트와 진단은 여전히 어려운 문제여서 이를 해결할 수 있는 효과적인 테스트 방법이 크게 요구된다. 본 논문에서는 time slot specification(TSS) 기반의 내장 전류감지기(Built-in Current Sensor)를 이용한 새로운 아날로그 회로의 테스트 기법을 제안한다. 또한 TSS에 기반 하여 고장 위치를 찾아내고 고장의 종류를 구별해 내는 방법을 제시한다. TSS 기법과 함께 제안하는 내장 전류감지기는 높은 고장 용이도와 높은 고장 검출을 그리고 아날로그 회로내 강고장과 약고장에 대한 높은 진단율을 갖는다. 제안하는 방법에서는 주출력과 전원단자등을 테스트 포인트로 사용하고 전류감지기를 자동 테스트 장치(Automatic Test Equipment)에 구성하므로써 테스트 포인트 선택과정의 복잡도를 줄일 수 있다. 내장 전류 감지기의 디지털 출력은 아날로그 IC 테스트를 위한 내장 디지털 테스트 모듈과 쉽게 연결된다.

• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 2004년도 춘계학술대회 논문집
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• pp.453-458
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• 2004

A capacitate sensor is a proper device for measuring high small displacement. General design parameters and procedure are discussed and a test sensor was built to have a measuring range of 100$\mu\textrm{m}$ and a sensitivity about 30nm. This sensor has too opposing electrode of comparably large area and has nominal gap distance about 150$\mu\textrm{m}$. So as to achieve a nano order displacement sensitivity, both sensor and target system have to be considered. This is important for the sensitivity can be achieved by minimizing a system total noise level in electronic type sensor application. Typical performance of the developed sensor is demonstrated in precision moving stage having 0.1$\mu\textrm{m}$ moving resolution.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제12권1호
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• pp.248-268
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• 2018

The performance of smartphone applications are usually constrained in user interactions due to resource limitation and it promises great opportunities to improve the performance by exploring the smartphone built-in and embedded sensing techniques. However, heterogeneity in techniques, semantic gap between sensor data and usable context, and complexity of contextual situations keep the techniques from seamless integration. Relevant studies mainly focus on feasibility demonstration of emerging sensing techniques, which rarely address both general architectures and comprehensive technical solutions. Based on a proposed functional model, this investigation provides a general architecture to deal with the dynamic context for context-aware automation and decision support. In order to take advantage of the built-in sensors to improve the performance of mobile applications, an ontology-based method is employed for context modelling, linguistic variables are used for heterogeneous context presentation, and semantic distance-based rule matching is employed to customise functions to the contextual situations. A case study on mobile application authentication is conducted with smartphone built-in hardware modules. The results demonstrate the feasibility of the proposed solutions and their effectiveness in improving operational efficiency.

• 전기학회논문지
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• 제56권2호
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• pp.361-366
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• 2007

In the distribution networks, it is necessary to develop small and light voltage and current sensor for compact and digitalized switchgears. For this purpose, some researches have been continuing till now, CT(current transformer) and VT(voltage transformer) are one of that research. But conventional CT and VT have some problems, that is, have big size and saturation characteristics because of used to iron core. In this paper, CS(current sensor) and VS(voltage sensor), have some merits measuring of current and voltage magnitude as a alternated conventional equipment, were studied. So, this paper shows the process CS and VS design method, equivalent circuit and output result, respectively. As a result of this test, proposed CS and VS have linearity for the output, no saturation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 A
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• pp.271-274
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• 2003

This paper presents a Built-in Current Sensor that detect defects in CMOS integrated circuits using the current testing technique. This scheme employs a cross-coupled connected PMOS transistors, it is used as a current comparator. Our proposed scheme is a negligible impart on the performance of the circuit undo. test (CUT). In addition, in the normal mode of the CUT not dissipation extra power, high speed detection time and applicable deep submicron process. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects. The entire area of the test chip is $116{\times}65{\mu}m^2$. The BICS occupies only $41{\times}17{\mu}m^2$ of area in the test chip. The area overhead of a BICS versus the entire chip is about 9.2%. The chip was fabricated with Hynix $0.35{\mu}m$ 2-poly 4-metal N-well CMOS technology.

• 전자공학회논문지B
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• 제32B권11호
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• pp.1434-1444
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• 1995

Current test has recently been known to be a promising testing method in CMOS VLSI because conventional voltage test can not make sure of the complete detection of bridging, gate-oxide shorts, stuck-open faults and etc. This paper presents a new BIC(built-in current sensor) for the internal current test in CMOS logic circuit. A single phase clock is used in the BIC to reduce the control circuitry of it and to perform a self- testing for a faulty current. The BIC is designed to detect the faulty current at the end of the clock period, so that it can test the CUT(circuit under test) with much longer critical propagation delay time and larger area than conventional BICs. The circuit is composed of 18 devices and verified by using the SPICE simulator.

• 센서학회지
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• 제31권6호
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• pp.411-417
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• 2022

In this paper, we propose a sensor with a C-shaped load cell to detect force change when a person sitting on the chair in an electrical transport-convenience vehicle is pushing ground by both heels. The load cell built in the vehicle is mechanically deformed by the vertical force owing to the human weight and the horizontal force by ground-pushing feet. The deformation rate of the load cell and its distribution are simulated using finite element analysis. In the simulation, the applied loads are preset in the range of 10 kg - 100 kg with a step size of 10 kg, and the ground-pushing force by feet is increased to 40 N with a step size of 5 N with respect to each applied load level. The resistance change of the load cell was observed to be linear in simulation as well as in measurement. the maximum difference between simulation and measurement was 0.89 % when the strain gauge constant was 2.243. The constant has a large influence on the difference. The proposed sensor was fabricated by connecting an instrument amplifier and a microcontroller to a load cell and used to detect the force by ground-pushing feet. To detect foot driving, the reference signal was set to 130% of the load, and the duration of the sensor output signal exceeding the reference signal was set to 0.6 s. In a test of a vehicle built with the proposed sensor, the footpushing force by the worker could be successfully detected even when the worker was working.

• 한국음향학회지
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• 제18권3호
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• pp.43-48
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• 1999

IDDQ 테스트는 CMOS 소자로 구성된 회로에서 기능 테스트로는 검출할 수 없는 결함을 찾아내어 회로의 신뢰성을 높여주는 전류테스트 방식이다. 본 논문에서는 IDDQ 테스트를 테스트 대상 칩 내에서 수행할 수 있는 내장전류감지(Built-In Current Sensor : BICS)회로를 설계하였다. 이 회로는 메모리의 IDDQ 테스트를 수행할 수 있도록 설계되었으며, 적은 트랜지스터를 사용하여 빠른 시간 내에 테스트를 수행할 수 있도록 구현하였다.