• Title/Summary/Keyword: Buffer size

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Implementation of a Shared Buffer ATM Switch Embedded Scalable Pipelined Buffer Memory (가변형 파이프라인방식 메모리를 내장한 공유버퍼 ATM 스위치의 구현)

  • 정갑중
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.6 no.5
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    • pp.703-717
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    • 2002
  • This paper illustrates the implementation of a scalable shared buffer asynchronous transfer mode (ATM) switch. The designed shared buffer ATM switch has a shared buffet of a pipelined memory which has the access time of 4 ns. The high-speed buffer access time supports a possibility of the implementation of a shared buffer ATM switch which has a large switching capacity. The designed switch architecture provides flexible switching performance and port size scalability with the independence of queue address control from buffer memory control. The switch size and the buffer size of the designed ATM switch can be reconfigured without serious circuit redesign. The designed prototype chip has a shared buffer of 128-cell and 4 ${\times}$ 4 switch size. It is integrated in 0.6um, double-metal, and single-poly CMOS technology. It has 80MHz operating frequency and supports 640Mbps per port.

Determination of Optimal Buffer Size for Semiconductor Production System using Harmony Search Algorithm (하모니서치 알고리즘을 이용한 반도체 공정의 최적버퍼 크기 결정)

  • Lee, Byeong-Gil;Byun, Minseok;Kim, Yeojin;Lee, Jonghwan
    • Journal of the Semiconductor & Display Technology
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    • v.19 no.4
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    • pp.39-45
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    • 2020
  • In the production process, the buffer acts as a buffer to alleviate some of the problems such as delays in delivery and process control failures in unexpected situations. Determining the optimal buffer size can contribute to system performance, such as increased output and resource utilization. However, there are difficulties in allocating the optimal buffer due to the complexity of the process or the increase in the number of variables. Therefore, the purpose of this research is proposing an optimal buffer allocation that maximizes throughput. First step is to design the production process to carry out the research. The second step is to maximize the throughput through the harmony search algorithm and to find the buffer capacity that minimizes the lead time. To verify the efficiency, comparing the ratio of the total increase in throughput to the total increase in buffer capacity.

Fast NAND Flash Memory System for Instruction Code Execution

  • Jung, Bo-Sung;Kim, Cheong-Ghil;Lee, Jung-Hoon
    • ETRI Journal
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    • v.34 no.5
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    • pp.787-790
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    • 2012
  • The objective of this research is to design a high-performance NAND flash memory system containing a buffer system. The proposed instruction buffer in the NAND flash memory consists of two parts, that is, a fully associative temporal buffer for temporal locality and a fully associative spatial buffer for spatial locality. A spatial buffer with a large fetching size turns out to be effective for serial instructions, and a temporal buffer with a small fetching size is devised for branch instructions. Simulation shows that the average memory access time of the proposed system is better than that of other buffer systems with four times more space. The average miss ratio is improved by about 70% compared with that of other buffer systems.

Effective Scalable Caching Algorithm by Minimizing Normalized Buffer Size over Constant-Bit-Rate Channel (일정한 채널 대역폭상에서 정규화 된 버퍼크기를 이용한 효율적인 선택적 캐슁 알고리즘)

  • Oh, Hyung-Rai;Song, Ywang-Jun
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.8B
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    • pp.535-540
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    • 2005
  • This paper presents a scalable caching algorithm of proxy server with the finite storage size minimizing client's buffer size and constant-bit-rate channel bandwidth. Under the general video traffic condition, it is observed that the amount of decreased client's buffer size and channel bandwidth after caching a video frame depends on the relative frame position in the time axis as the frame size. Based on this fact, we propose an effective caching algorithm to select the cached frames by using the normalized buffer size. Finally, experimental results are provided to show the superior performance of the proposed alghrithm.

A Multimedia Data Management Technique Using Variable Size Buffer (가변 크기 버퍼를 이용한 멀티미디어 데이타 버퍼 관리 기법)

  • Jo, Yeong-Seop;Kim, Jae-Hong;Bae, Hae-Yeong
    • The Transactions of the Korea Information Processing Society
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    • v.3 no.6
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    • pp.1375-1385
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    • 1996
  • As there has been much demands for processing multimedia data, a storage manager for multimedia data makes much effects on system performance. Because the size of multimedia data is usually very large, disk I/O for the data consumes much time and causes the system performance to be decreased. Therefore, it makes a better effect on system performance that a multimedia data storage manager decreases its disk I/O by the buffer management of multimedia data. This paper proposes a buffer management technique which allocates the buffer to be equal to its corresponding segment which consists of physically continuous disk page set and is disk management unit for multimedia data in many multimedia data storage manager. As the size of buffer varies, it also proposes a buffer replacement policy which consider not only reference behavior of buffer but also buffer size The proposed multimedia data buffer management technique is implemented in KORED/STORM which is a storage manager for multimedia data.

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A Study on the Multiplexing of ISDN D-channel using Statistical Multiplexer (총계적 다중 방식을 이용한 ISDN D채널 다중화에 관한 연구)

  • 구제길;김영철;이호준;조규섭;박병철;김병찬
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.11 no.4
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    • pp.268-279
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    • 1986
  • Recently, the improtance of the ISDN has been emphasized for the new services in the future information society. In this paper, new application of statistical multiplexer which can be used for CCITT D-channel multiplexing is suggested. The basic architecture of statistical multiplexer which can interleave eleven 16Kbps D-channels into one 64Kbps B-channel is also proposed. The necessary buffer size was estimated by computer simulation considering data traffic intensity, signal arrival length distribution and buffer overflow probability. Based on this buffer size, the basic architecture of the statistical multiplexer has been survetyed and hardware design principles are also studied.

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The Efficient Buffer Size in A Dual Flash Memory Structure with Buffer System (이중 NAND 플래시 구조의 버퍼시스템에서 효율적 버퍼 크기)

  • Jung, Bo-Sung;Lee, Jung-Hoon
    • IEMEK Journal of Embedded Systems and Applications
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    • v.6 no.6
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    • pp.383-391
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    • 2011
  • As we know the effects of cache memory research, instruction and data caches can be separated for higher performance with Harvard CPUs. In this paper, we shows the efficiency of buffer system in the instruction and data flash storage medium. And we analyzed characteristics of the data and instruction flash and evaluated the performance. Finally, we propose the best buffer structure with an optimal block size and buffer size for the instruction and data flash.

A Dynamic Buffer Allocation Scheme in Video-on-Demand System (주문형 비디오 시스템에서의 동적 버퍼 할당 기법)

  • Lee, Sang-Ho;Moon, Yang-Sae;Whang, Kyu-Young;Cho, Wan-Sup
    • Journal of KIISE:Computer Systems and Theory
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    • v.28 no.9
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    • pp.442-460
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    • 2001
  • In video-on-demand(VOD) systems it is important to minimize initial latency and memory requirements. The minimization of initial latency enables the system to provide services with short response time, and the minimization of memory requirements enables the system to service more concurrent user requests with the same amount of memory. In VOD systems, since initial latency and memory requirement increase according to the increment of buffer size allocated to user requests, the buffer size allocated to user requests must be minimized. The existing static buffer allocation scheme, however, determines the buffer size based on the assumption that thy system is in fully loaded state. Thus, when the system is in partially loaded state, the scheme allocates user requests unnecessarily large buffers. This paper proposes a dynamics buffer allocation scheme that allocates user requests the minimum buffer size in fully loaded state as well as a partially loaded state. This scheme dynamically determines the buffer size based on the number of user requests in service and the number of user requests arriving while servicing current requests. In addition, through analyses and simulations, this paper validates that the dynamics buffer allocation outperforms the statics buffer allocation in initial latency and the number of concurrent user requests that can be supported. Our simulation results show that, in proportion to the static buffer allocation scheme, the dynamic buffer allocation scheme reduces the average initial latency by 29%~65%, and in a systems having several disks. increases the average number of concurrent user requests by 48%~68%. Our results show that the dynamic buffer allocation scheme significantly improves the performance and reduce the capacity requirements of VOD systems.

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Estimating the Optimal Buffer Size on Mobile Devices for Increasing the Quality of Video Streaming Services (동영상 재생 품질 향상을 위한 최적 버퍼 수준 결정)

  • Park, Hyun Min
    • The Journal of the Korea Contents Association
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    • v.18 no.3
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    • pp.34-40
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    • 2018
  • In this study, the optimal buffer size is calculated for seamless video playback on a mobile device. Buffer means the memory space for multimedia packet which arrives in mobile device for video play such as VOD service. If the buffer size is too large, latency time before video playback can be longer. However, if it is too short, playback service can be paused because of shortage of packets arrived. Hence, the optimal buffer size insures QoS of video playback on mobile devices. We model the process of buffering into a discret-time queueing model. Mean busy period length and mean waiting time of Geo/G/1 queue with N-policy is analyzed. After then, we uses the main performance measures to present numerical examples to decide the optimal buffer size on mobile devices. Our results enhance the user satisfaction by insuring the seamless playback and minimizing the initial delay time in VOD streaming process.

Impact of playout buffer dynamics on the QoE of wireless adaptive HTTP progressive video

  • Xie, Guannan;Chen, Huifang;Yu, Fange;Xie, Lei
    • ETRI Journal
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    • v.43 no.3
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    • pp.447-458
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    • 2021
  • The quality of experience (QoE) of video streaming is degraded by playback interruptions, which can be mitigated by the playout buffers of end users. To analyze the impact of playout buffer dynamics on the QoE of wireless adaptive hypertext transfer protocol (HTTP) progressive video, we model the playout buffer as a G/D/1 queue with an arbitrary packet arrival rate and deterministic service time. Because all video packets within a block must be available in the playout buffer before that block is decoded, playback interruption can occur even when the playout buffer is non-empty. We analyze the queue length evolution of the playout buffer using diffusion approximation. Closed-form expressions for user-perceived video quality are derived in terms of the buffering delay, playback duration, and interruption probability for an infinite buffer size, the packet loss probability and re-buffering probability for a finite buffer size. Simulation results verify our theoretical analysis and reveal that the impact of playout buffer dynamics on QoE is content dependent, which can contribute to the design of QoE-driven wireless adaptive HTTP progressive video management.