• 한국조경학회지
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• 제33권6호
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• pp.90-97
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• 2006

The effects of a green buffer zone to protect a residential area from air pollution from industrial facilities and traffic was examined by analyzing the case of a green buffer zone in the Shiwha industrial complex. The green buffer zone is 175 m wide. The intent was to assess the dispersion patterns of atmospheric air pollutants and the reduction in concentration around the green buffer zone. To measure atmospheric sulfur dioxide$(SO_2)$ and nitrogen dioxide$(NO_2)$ concentration, badge-type passive samplers were used and set up at 76 locations in order to measure the concentration of air pollutants with respect to the spatial dispersion. The weighted mean values of $SO_2\;and\;NO_2$ concentration were $3\~57 ppb\;and\;18\~62 ppb$ and the differences among the green buffer zone, the industrial area and the residential areas were $0.7\~1.1 ppb$. Mean values of atmospheric concentrations of $NO_2$ were similar in industrial and, residential areas and the green buffer zone. Results of the study show that the effect of the green buffer zone on reducing the dispersion of air pollutants was very low. This study also recommends that micro-climate, i.e., wind direction should be considered as a factor for planning and design of green buffer zones.

• 전기전자학회논문지
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• 제7권2호
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• pp.260-264
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• 2003

네트워크의 성능 향상에 영향을 미치는 여러 요소 중에서, 본 연구에서는 NIC(Network Interface Card) 버퍼 사이즈(Buffer Size)가 웹 서버와 LAN(Local Area Netwok)에 어떤 영향을 미치는지를 분석하였다. 버퍼 사이즈의 조절을 통해서 내부 네트워크의 패킷 분실율, 처리량, RTT(Round Trip Time), 수신율의 변화를 NS-2를 사용하여 시뮬레이션 해보고 그 결과를 비교하여 이더넷(Ethernet)에서의 웹 트래픽에 미치는 영향을 분석하였다.

• Transactions on Electrical and Electronic Materials
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• 제18권3호
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• pp.125-128
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• 2017

This study is on how ohmic area etching affects the buffer breakdown voltage of AlGaN/GaN HEMT. The surface morphology of the ohmic metal can be improved by whole etching on the ohmic area. The buffer breakdown voltages of the samples with whole etching on the ohmic area were improved by the suppression of the metal spikes formed under the ohmic contact regions during high-temperature annealing. The samples with selective etching on the ohmic area were investigated for comparison. In addition, the buffer leakage currents were measured on the different radii of the wafer, and the uniformity of the buffer leakage currents on the wafer were investigated by PL mapping measurement.

• 한국정보과학회논문지:시스템및이론
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• 제27권7호
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• pp.684-694
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• 2000

저 전력회로의 설계를 위해서, 전체 회로의 면적을 줄임으로써 용량성 부하(capacitance)값을 줄이는 방법으로 적절한 트랜지스터를 선택하여 사이징하는 방법을 이용할 수 있는데, 이 때 트랜지스터 사이징을 수행하면서 적당한 위치에 버퍼를 삽입하여주면 더 좋은 결과를 가져올 수 있다. 본 논문은 TILOS 알고리즘을 이용하여 트랜지스터 사이징(sizing)을 수행하는 동시에 버퍼의 삽입을 수행하는 알고리즘 두 가지를 소개하고 이 두 방법을 비교한다. 그 첫 번째 방법은 Template Window를 이용하여 직접 시뮬레이션하는 방법이고 다른 하나는 보외법(Extrapolation)을 이용하는 방법이다. 이와 같이 버퍼를 삽입하면서 트랜지스터 사이징을 수행한 결과, 버퍼를 삽입하지 않을 때 보다 10-20%의 면적감소를 얻었을 수 있었으며 보외법을 이용한 방법 보다 Template Window를 이용했을 때 더 좋은 결과를 얻을 수 있었다.

• 한국환경복원기술학회지
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• 제13권6호
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• pp.1-12
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• 2010

This study aims at analyzing the development status of surroundings of natural environment conservation areas and securing an adequate distance from development activities to conserve natural environment conservation areas efficiently or developing an improvement plan for setting conservation areas. Findings from the study shows that 1) rather than simply designating a legal natural environment conservation area, a conceptual scope approach of a "core area", "buffer area", and "transition area" such as in zoning of a "biosphere reserve" by UNESCO is recommended; 2) when setting an adequate range in a natural environment conservation area, it should be set by fully considering locational situation and the regional and environmental features of surroundings rather than setting a certain distance uniformly; 3) instead of designating wetlands only as a conservation area, entry and exit areas should be also included as buffer areas and in the case of wild animals, not only habitats but also feeding areas should be designated as conservation areas; and 4) an adequate horizontal separation space is important in the case of ground development, but for natural resources related to subterranean water and geological situation such as wetlands, an adequate vertical separation space should be fully considered.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1512-1515
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• 1987

The buffer circuit having minimum delay time is designed and analyzed in this paper. Considering the parasitic components of the MOS transistor, the optimal transistor size ratio between the individual buffer stages is presented. This paper's result is better than that of the Mead and Conway's analysis [1] with respect to both delay time and total area that buffer occupies.

• 건축역사연구
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• 제16권5호
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• pp.55-66
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• 2007

Through analysing on construction cases of stupa built in A.D. 7,8th, I have researched about these : constructive methods of inner soil of stupa, spatial compositions, characteristics of structures, arrangements of inner soil and etc. And cases analysed are six ; Mireuksajiseoktap(stone pagoda of Mireuksa Temple site), Gameunsajisamcheumgseoktap(three storied stone pagoda of Gameunsa Temple site), Goseonsajisamcheungseoktap(three storied stone pagoda of Goseonsa Temple site), Wolseong nawolliocheungseoktap(five storied stone pagoda in Nawonri, Wolseong), Guksagokseoktap(three storied stone pagoda in Guksa valley), Giamgokseoktap(three storied stone pagoda in Giam valley). Additionally we researched about inner soil of Sacheonwangsaji tapji(basement of stone stupa site in Sacheonwang Temple site) to speculate on composition of Synthetically, the foundation could be divided as core space and outer space. ; the former as structural function and the latter as ornamental function. And the core area could be divided again as center column space and buffer space. The relationship between core spaces and its formation are as belows; First, according to the area of foundation and scale of stone pagoda, formations of core are differed. As the scale of stone pagoda goes bigger, and the area of foundation goes larger, the structure of stone pagoda comprised by center column type and layered-core which endure upper load independently. On the contrary, as the scale of stone pagoda goes smaller, and the area of foundation goes lesser, the structure of stone pagoda tend to use only center column to endure upper part. Second, spatial composition of core area is comprised as two spaces, one which endure upper load and buffer space which absorb side pressure and upper pressure. The buffer space tend to be used in case of those structures which could not endure side pressure or have lots of joint. In some cases, it was located below the cover stone of foundation and gained upper load. And in case that have not gained pressure from side stone, the buffer space are comprised by smalle stone or roof tile to get structural supplement.

• 대한전자공학회논문지
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• 제25권5호
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• pp.509-521
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• 1988

In the designs of integrated circuits, the buffer circuits used for driving a large capacitive load from minimum-structured logic circuit outputs have important effects upon system throughputs. Therefore it is important to optimize the buffer circuits. In this paper, the principle of designing CMOS buffer circuits which have the minimum delay and drive the given capacitive load is discussed. That is, the effects of load capacitance upon rise time, fall time, and delay of the CMOS inverter and the effects of parasitic capacitances are finely analysed to calculate the requested minimum-delay CMOS buffer condition. This is different from the method by C.A. Mead et. al.[2.3.4.]which deals with passive-load-nMOS buffers. Large channel width MOS transistor stages are necessary to drive a large capacitive load. The effects of polysilicon gate resistances of such large stages upon delay are also analysed.And, the area of buffer circuits designed by the proposed method is smaller than that of buffer circuits designed by C.A. Mead's method.

• ETRI Journal
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• 제25권5호
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• pp.297-304
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• 2003

A multimedia SoC often requires a large internal buffer, because it must store the whole search window to reduce the huge I/O bandwidth of motion estimation. However, the silicon area of the internal buffer increases tremendously as the search range becomes larger. This paper proposes a new method that greatly reduces the internal buffer size of a multimedia SoC while the computational cost, I/O bandwidth, and image quality do not change. In the proposed method, only the overlapped parts of search windows for consecutive macroblocks are stored in the internal buffer. The proposed method reduces the internal buffer. The proposed method reduces the internal buffer size to 1/5.0 and 1/8.8 when the search range is ${\pm}64{\times}{\pm}$64 and ${\pm}128{\times}{\pm}$128, respectively.

• 한국환경생태학회지
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• 제24권2호
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• pp.157-165
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• 2010

본 연구는 일본 고베시 로코아일랜드 완충녹지의 공간기능별 지형구조, 식재개념, 식재구조를 조사분석하여 해안매립도시의 토지이용을 고려한 완충녹지 식재기법 연구 기초자료를 제공하고자 수행하였다. 로코아일랜드(총면적 580ha)는 대규모 완충녹지를 박스형으로 조성하여 외곽부의 항만물류 산업용지와 도시내부 도시기능용지로 구획되었다. 완충녹지 지형구조는 편향마운딩형, 병렬마운딩형, 복합마운딩형이었고, 북쪽의 녹지폭은 50m, 동쪽의 녹지폭은 8~32m, 서쪽의 녹지폭은 37.5m, 경사도는 $18\sim25^{\circ}$, 성토고는 2~15m이었다. 공간기능별 재개념은 해안측 사면부는 경관식재와 완충식재, 도시내부는 경관식재와 녹음식재를 적용하였다. 북측 완충녹지 식재구조 조사결과, 종가시나무, 녹나무, 후박나무, 녹보리똥나무 등 난온대 상록활엽수를 식재하였고, $100mm^2$단위의 종수 및 식재밀도는 최대 교목 9종 22주, 아교목 9종 15주, 관목 3종 67주로 전 층위 14종 104주이었다. 녹피율은 교목층 69~139%, 아교목층 26~38%, 관목층 6~7%, 전 층위 101~184%, 녹지용적계수는 교목층 $1.40\sim3.12m^3/m^2$, 아교목층 $0.43\sim0.55m^3/m^2$, 관목층 $0.06m^3/m^2$, 전 층위 $1.89\sim3.73m^3/m^2$이었다.