• Title/Summary/Keyword: Buffer area

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Effect of Green Buffer Zone in Reducing Gaseous Air Pollutants in the Shiwha Industrial Area (시화공단 완충녹지대의 대기오염물질 저감 효과 분석)

  • Song Young-Bae
    • Journal of the Korean Institute of Landscape Architecture
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    • v.33 no.6 s.113
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    • pp.90-97
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    • 2006
  • The effects of a green buffer zone to protect a residential area from air pollution from industrial facilities and traffic was examined by analyzing the case of a green buffer zone in the Shiwha industrial complex. The green buffer zone is 175 m wide. The intent was to assess the dispersion patterns of atmospheric air pollutants and the reduction in concentration around the green buffer zone. To measure atmospheric sulfur dioxide$(SO_2)$ and nitrogen dioxide$(NO_2)$ concentration, badge-type passive samplers were used and set up at 76 locations in order to measure the concentration of air pollutants with respect to the spatial dispersion. The weighted mean values of $SO_2\;and\;NO_2$ concentration were $3\~57 ppb\;and\;18\~62 ppb$ and the differences among the green buffer zone, the industrial area and the residential areas were $0.7\~1.1 ppb$. Mean values of atmospheric concentrations of $NO_2$ were similar in industrial and, residential areas and the green buffer zone. Results of the study show that the effect of the green buffer zone on reducing the dispersion of air pollutants was very low. This study also recommends that micro-climate, i.e., wind direction should be considered as a factor for planning and design of green buffer zones.

The Effect of NIC Buffer Size of Web Server on the Performance of LAN (웹 서버의 NIC 버퍼 사이즈가 LAN 성능에 미치는 영향)

  • Kim, Jin-Hee;Sin, Bum-Suk;Kwon, Kyung-Hee
    • Journal of IKEEE
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    • v.7 no.2 s.13
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    • pp.260-264
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    • 2003
  • Among many factors to affect the network performance, this paper analyses how the buffer size of NIC(Network Interface Card) can affect web server and LAN(Local Area Network). We use the ns-2 which is defacto network simulation tool to observe the changes in drop rate, throughput, RTT(Round Trip Time), effective throughput depending on varying buffer sizes. And we analyse the effect of NIC buffer size on the web traffic in Ethernet.

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Effects of Ohmic Area Etching on Buffer Breakdown Voltage of AlGaN/GaN HEMT

  • Wang, Chong;Wel, Xiao-Xiao;Zhao, Meng-Di;He, Yun-Long;Zheng, Xue-Feng;Mao, Wei;Ma, Xiao-Hua;Zhang, Jin-Cheng;Hao, Yue
    • Transactions on Electrical and Electronic Materials
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    • v.18 no.3
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    • pp.125-128
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    • 2017
  • This study is on how ohmic area etching affects the buffer breakdown voltage of AlGaN/GaN HEMT. The surface morphology of the ohmic metal can be improved by whole etching on the ohmic area. The buffer breakdown voltages of the samples with whole etching on the ohmic area were improved by the suppression of the metal spikes formed under the ohmic contact regions during high-temperature annealing. The samples with selective etching on the ohmic area were investigated for comparison. In addition, the buffer leakage currents were measured on the different radii of the wafer, and the uniformity of the buffer leakage currents on the wafer were investigated by PL mapping measurement.

Transistor Sizing and Buffer Insertion Algorithms for Optimum Area under Delay Constraint (지연 제약 하에서 면적의 최적화를 위한 트랜지스터 사이징과 버퍼 삽입 알고리즘)

  • Lee, Sung-Kun;Kim, Ju-Ho
    • Journal of KIISE:Computer Systems and Theory
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    • v.27 no.7
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    • pp.684-694
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    • 2000
  • For designing circuits for low power systems, the capacitance is an important factor for the power dissipation. Since the capacitance of a gate is proportional to the area of the gate, we can reduce the total power consumption of a circuit by reducing the total area of gates, where total area is a simple sum of all gate areas in the circuit. To reduce the total area, transistor resizing can be used. While resizing transistors, inserting buffer in the proper position can help reduce the total area. In this paper we propose two methods for concurrent transistor sizing and buffer insertion. One method uses template window simulation and the other uses extrapolation. Experimental results show that concurrent transistor sizing with buffer insertion achieved 10-20% more reduction of the total area than when it was done without buffer insertion and template window simulation is more efficient than extrapolation.

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Basic Study on Criteria for Setting Natural Conservation Area (자연환경 보전지역 설정기준에 관한 기초연구)

  • Sung, Hyun-Chan;Hwang, So-Young;Chae, Mie-Oak;Park, Eun-Suk
    • Journal of the Korean Society of Environmental Restoration Technology
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    • v.13 no.6
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    • pp.1-12
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    • 2010
  • This study aims at analyzing the development status of surroundings of natural environment conservation areas and securing an adequate distance from development activities to conserve natural environment conservation areas efficiently or developing an improvement plan for setting conservation areas. Findings from the study shows that 1) rather than simply designating a legal natural environment conservation area, a conceptual scope approach of a "core area", "buffer area", and "transition area" such as in zoning of a "biosphere reserve" by UNESCO is recommended; 2) when setting an adequate range in a natural environment conservation area, it should be set by fully considering locational situation and the regional and environmental features of surroundings rather than setting a certain distance uniformly; 3) instead of designating wetlands only as a conservation area, entry and exit areas should be also included as buffer areas and in the case of wild animals, not only habitats but also feeding areas should be designated as conservation areas; and 4) an adequate horizontal separation space is important in the case of ground development, but for natural resources related to subterranean water and geological situation such as wetlands, an adequate vertical separation space should be fully considered.

A Design of The Buffer Circuit having Minimum Delay Time (최소 delay를 갖는 buffer 회로의 설계)

  • Kang, In-Yup;Song, Min-Kyu;Kim, Won-Chan
    • Proceedings of the KIEE Conference
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    • 1987.07b
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    • pp.1512-1515
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    • 1987
  • The buffer circuit having minimum delay time is designed and analyzed in this paper. Considering the parasitic components of the MOS transistor, the optimal transistor size ratio between the individual buffer stages is presented. This paper's result is better than that of the Mead and Conway's analysis [1] with respect to both delay time and total area that buffer occupies.

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A study on characteristics of composition method of inner foundation in stone stupa (석탑 기단부 적심구성방법에 대한 특성 고찰 - $7{\sim}8$세기 석탑 중 해체 수리한 석탑을 중심으로 -)

  • Chung, Hae-Doo;Jang, Suk-Ha
    • Journal of architectural history
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    • v.16 no.5
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    • pp.55-66
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    • 2007
  • Through analysing on construction cases of stupa built in A.D. 7,8th, I have researched about these : constructive methods of inner soil of stupa, spatial compositions, characteristics of structures, arrangements of inner soil and etc. And cases analysed are six ; Mireuksajiseoktap(stone pagoda of Mireuksa Temple site), Gameunsajisamcheumgseoktap(three storied stone pagoda of Gameunsa Temple site), Goseonsajisamcheungseoktap(three storied stone pagoda of Goseonsa Temple site), Wolseong nawolliocheungseoktap(five storied stone pagoda in Nawonri, Wolseong), Guksagokseoktap(three storied stone pagoda in Guksa valley), Giamgokseoktap(three storied stone pagoda in Giam valley). Additionally we researched about inner soil of Sacheonwangsaji tapji(basement of stone stupa site in Sacheonwang Temple site) to speculate on composition of Synthetically, the foundation could be divided as core space and outer space. ; the former as structural function and the latter as ornamental function. And the core area could be divided again as center column space and buffer space. The relationship between core spaces and its formation are as belows; First, according to the area of foundation and scale of stone pagoda, formations of core are differed. As the scale of stone pagoda goes bigger, and the area of foundation goes larger, the structure of stone pagoda comprised by center column type and layered-core which endure upper load independently. On the contrary, as the scale of stone pagoda goes smaller, and the area of foundation goes lesser, the structure of stone pagoda tend to use only center column to endure upper part. Second, spatial composition of core area is comprised as two spaces, one which endure upper load and buffer space which absorb side pressure and upper pressure. The buffer space tend to be used in case of those structures which could not endure side pressure or have lots of joint. In some cases, it was located below the cover stone of foundation and gained upper load. And in case that have not gained pressure from side stone, the buffer space are comprised by smalle stone or roof tile to get structural supplement.

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the Design Methodology of Minimum-delay CMOS Buffer Circuits (최소 지연시간을 갖는 CMOS buffer 회로의 설계 기법)

  • 강인엽;송민규;이병호;김원찬
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.5
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    • pp.509-521
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    • 1988
  • In the designs of integrated circuits, the buffer circuits used for driving a large capacitive load from minimum-structured logic circuit outputs have important effects upon system throughputs. Therefore it is important to optimize the buffer circuits. In this paper, the principle of designing CMOS buffer circuits which have the minimum delay and drive the given capacitive load is discussed. That is, the effects of load capacitance upon rise time, fall time, and delay of the CMOS inverter and the effects of parasitic capacitances are finely analysed to calculate the requested minimum-delay CMOS buffer condition. This is different from the method by C.A. Mead et. al.[2.3.4.]which deals with passive-load-nMOS buffers. Large channel width MOS transistor stages are necessary to drive a large capacitive load. The effects of polysilicon gate resistances of such large stages upon delay are also analysed.And, the area of buffer circuits designed by the proposed method is smaller than that of buffer circuits designed by C.A. Mead's method.

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Pipelined Macroblock Processing to Reduce Internal Buffer Size of Motion Estimation in Multimedia SoCs

  • Lee, Seong-Soo
    • ETRI Journal
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    • v.25 no.5
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    • pp.297-304
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    • 2003
  • A multimedia SoC often requires a large internal buffer, because it must store the whole search window to reduce the huge I/O bandwidth of motion estimation. However, the silicon area of the internal buffer increases tremendously as the search range becomes larger. This paper proposes a new method that greatly reduces the internal buffer size of a multimedia SoC while the computational cost, I/O bandwidth, and image quality do not change. In the proposed method, only the overlapped parts of search windows for consecutive macroblocks are stored in the internal buffer. The proposed method reduces the internal buffer. The proposed method reduces the internal buffer size to 1/5.0 and 1/8.8 when the search range is ${\pm}64{\times}{\pm}$64 and ${\pm}128{\times}{\pm}$128, respectively.

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Planting Method of Buffer Green Space in the Reclaimed Seaside Areas, Rokko Island, Kobe, Japan (일본 고베시(신호시(神戶市)) 로코(육갑(六甲))아일랜드 임해매립지의 완충녹지 식재기법 연구)

  • Han, Bong-Ho;Kim, Jong-Yup;Choi, Jin-Woo;Cho, Yong-Hyeon
    • Korean Journal of Environment and Ecology
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    • v.24 no.2
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    • pp.157-165
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    • 2010
  • This study was carried out to suggest the basic data of planting method for construction of buffer green space based on the land use in case of reclaimed land by analyzing land structure, planting concept, and planting structure in buffer green space, Rokko Island, Kobe, Japan. Rokko Island(total area: 580ha) is divided into port and logistics industry area and urban area by constructing the box type large-scale buffer green space. The land structure of buffer green space were biased mounding type, parallel mounding type, and complex mounding type. The width of buffer green space was 50meters in case of northern area, from 28 to 32meters in case of eastern area, and 37.5meters in case of western area, and the slope of that was from 18 to 25 degrees and the height of that was from 2 to 15meters. There were applied landscape and buffer planting concept on the sea side area of northern buffer green space, on the other hand landscape and shade planting concept on the Inner city side area of that. According to the result of planting structure analysis of northern buffer green space, the main woody species were those of deciduous-evergreen species grow in warm-temperate forest zone such as Quercus glauca, Cinnamomum camphora, Machilus thunbergii, Elaeagnus maritima. The results of maximum number of species and planting density by $100mm^2$ was that 9 species 22 individuals in canopy layer, 9 species 15 individuals in understory layer, 3 species 67 individuals in shrub layer, and 14 species 104 individuals in total. The plant coverage of northern buffer green space based on the ecological planting method was from 69 to 139% in case of canopy layer, from 26 to 38% in case of understory layer, from 6 to 7% in case of shrub layer, and from 101 to 184% in total. Index of plant crown volume of northern buffer green space based on the ecological planting method was from 1.40 to $3.12m^3/m^2$ in case of canopy layer, from 0.43 to $0.55m^3/m^2$ in case of understory layer, $0.06m^3/m^2$ in case of shrub layer, and from 1.89 to $3.73m^3/m^2$ in total.