• Journal of the Korea Institute of Military Science and Technology
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• v.5 no.2
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• pp.103-115
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• 2002

This paper describes the results on the design and implementation of large capacity cable checking system using I/O buffer method. The I/O buffer module which has feedback loops with input and output buffers is designed with logic gate in the VME board and controlled by MPC860 microprocessor. So this system can check a lot of cable at the same time with less size and less processing time than that of relay matrix method with the A/D converter. The size of the I/O buffer module can be variable according to the number of cable. And any type of cable can be checked even if the pin assignment of cable is changed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.790-793
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• 2000

We have fabricated good quality superconducting YBa$_2$Cu$_3$$O_{7-x}$(YBCO) thin films on Hastelloy(Ni-Cr-Mo alloys) metallic substrates with CeO$_2$and BaTiO$_3$buffer layers in-situ by pulsed laser deposition in a multi-target processing chamber. YBCO film with CeO$_2$ single buffer layer shows T$_{c}$ of 71.64 K and the grain size less than 0.1 ${\mu}{\textrm}{m}$. When BaTiO$_3$is used as a single buffer layer, the grain size of YBCO is observed to be larger than that of YBCO/CeO$_2$by 200 times and the transition temperature of the film is enhanced to be about 84 K. CeO$_2$/BaTiO$_3$double buffer layer has been adopted to enhance the superconducting properties, which results in the enhancement of the critical temperature and the critical current density to be about 85 K and 8.4 $\times$ 10$^4$ A/cm$^2$ at 77 K, respectively mainly due to the enlargement of the grain size of YBCO film.ilm.

• Journal of Korean Institute of Industrial Engineers
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• v.16 no.2
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• pp.81-89
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• 1990

Transfer pricing mechanism is applied to the problem of input buffer size in the context of interfacing a flexible manufacturing system with multiple following production lines. The size of the input buffers can be determined economically by using non-linear transfer pricing either in a decentralized organization or in a centralized organization. Under the certain conditions, input buffer size determined from this non-linear transfer pricing is more economical than the traditional economic lot size model. The benefit comes from transferring part of FMS' inventory to the following production lines. And this non-linear transfer pricing makes sense if the FMS' unit inventory holding cost is high enough.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.10 no.1
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• pp.36-41
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• 2000

We studied the exchange anisotropy of Ni-Fe/Co-Fe/Mn-Ir/Cu/buffer/Si multilayers using D.C magnetron sputtering technique. Generally, Ni-Fe/Mn-Ir/buffer(Cu)/Si multilayers cannot pin the ferromagnetic layer for the lower exchange biased field. We got $H_{ex}$ ex/ increased by two times, after using Cu/Ta as buffer layer to get larger grain size of Mn-Ir layer and inserting very thin Co-Fe layer between the Ni-Fe layer and the Mn-Ir layer to get improved grain-to-grain epitaxy relation at the interface between Ni-Fe layer and Mn-Ir layer. The variation of $H_{ex}$ by thickness of Mn-Ir layer in ferromagnete/Mn-Ir/buffer/Si multilayers is different to that in Mn-Ir/ferromagnete/buffer/Si multilayers, because the volume distribution of grain size of Mn-Ir layer and the exchange energy at the interface between the Mn-Ir and the ferromagnetic layers is different for stacking sequence.

• The Journal of the Korea Contents Association
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• v.5 no.5
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• pp.248-254
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• 2005

The existing buffer management scheme is caused by with burstness characteristic of the TCP traffic and with only the transmission which is not loss it provides the smallest transmission rate guarantee where the GFR demands and a fair characteristic. In order to provide a high fair characteristic from the dissertation which it sees with the smallest transmission rate guarantee where the GFR demands it proposed the existing buffer algorithm which applies a Fuzzy mechanism in the existing buffer management technique. The proposed algorithm decides a packet disuse used by three parameters which are composed of tagging information, the buffer usage, and the load of VC. Simulation results shows that the fairness and goodput of the proposed algorithm were excellent where the size of MCR will become larger, from the switch the Double-EPD or the DFBA was visible a similar efficiency even from size change of the buffer. The algorithm which is proposed provides a good throughput and a fair characteristic.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.6 no.2
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• pp.683-701
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• 2012

IEEE 802.11 standard has achieved huge success in the past decade and is still under development to provide higher physical data rate and better quality of service (QoS). An important problem for the development and optimization of IEEE 802.11 networks is the modeling of the MAC layer channel access protocol. Although there are already many theoretic analysis for the 802.11 MAC protocol in the literature, most of the models focus on the saturated traffic and assume infinite buffer at the MAC layer. In this paper we develop a unified analytical model for IEEE 802.11 MAC protocol in ad hoc networks. The impacts of channel access parameters, traffic rate and buffer size at the MAC layer are modeled with the assistance of a generalized Markov chain and an M/G/1/K queue model. The performance of throughput, packet delivery delay and dropping probability can be achieved. Extensive simulations show the analytical model is highly accurate. From the analytical model it is shown that for practical buffer configuration (e.g. buffer size larger than one), we can maximize the total throughput and reduce the packet blocking probability (due to limited buffer size) and the average queuing delay to zero by effectively controlling the offered load. The average MAC layer service delay as well as its standard deviation, is also much lower than that in saturated conditions and has an upper bound. It is also observed that the optimal load is very close to the maximum achievable throughput regardless of the number of stations or buffer size. Moreover, the model is scalable for performance analysis of 802.11e in unsaturated conditions and 802.11 ad hoc networks with heterogenous traffic flows.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.11
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• pp.2828-2835
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• 1996

In this paper we propose a new shaping algorithm which can control the shaping delay and the output buffer size based on the leaky bucket counter with a threshold value. This paper assumes that input traffic of the proposed shaping algorithm is the worst case traffic tolerated by the continuous leaky bucket algorithm and claracterizes traffic patterns that can depart from our shaping algorithm. We also compare shaping delay and output buffer size of the proposed algorithm with the existing shaping algorithm without a threshold value. Our results show that the proposed shaping algorithm can easily manage the shaping delay and output buffer size than any other mechanism.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1512-1515
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• 1987

The buffer circuit having minimum delay time is designed and analyzed in this paper. Considering the parasitic components of the MOS transistor, the optimal transistor size ratio between the individual buffer stages is presented. This paper's result is better than that of the Mead and Conway's analysis [1] with respect to both delay time and total area that buffer occupies.

• Journal of the Korea Society of Computer and Information
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• v.16 no.2
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• pp.1-8
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• 2011

NAND type Flash memory has performing much researches for a hard disk substitution due to its low power consumption, cheap prices and a large storage. Especially, the NAND type flash memory is using general buffer systems of a cache memory for improving overall system performance, but this has shown a tendency to emphasize in terms of data. So, our research is to design a high performance instruction NAND type flash memory structure by using a buffer system. The proposed buffer system in a NAND flash memory consists of two parts, i.e., a fully associative temporal buffer for branch instruction and a fully associative spatial buffer for spatial locality. The spatial buffer with a large fetching size turns out to be effective serial instructions, and the temporal buffer with a small fetching size can achieve effective branch instructions. According to the simulation results, we can reduce average miss ratios by around 77% and the average memory access time can achieve a similar performance compared with the 2-way, victim and fully associative buffer with two or four sizes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.45-52
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• 2011

Flash memory is becoming widely prevalent in various area due to high performance, non-volatile features, low power, and robust durability. As price-per-bit is decreased, NAND flash based SSDs (Solid State Disk) have been attracting attention as the next generation storage device, which can replace HDDs (Hard Disk Drive) which have mechanical properties. Especially for the single package SSD, if channel number or FIFO buffer size per channel increases to improve performance, the size of a controller and I/O pin count will increase linearly with channel numbers and form factor will be affected. We propose a novel technique which can minimize form factor by optimizing the number of NAND flash channels and the size of interface FIFO buffer in the SSD. For SSD with 10 channel and double buffer, the experimental results show that buffer block size can be reduced about 73% without performance degradation and total size of a controller can be reduced about 40% because control block per channel and I/O pin count decrease according to decrease channel number.