• 제목/요약/키워드: Buffer

검색결과 6,282건 처리시간 0.037초

Petri Net Modeling and Analysis for Periodic Job Shops with Blocking

  • Lee, Tae-Eog;Song, Ju-Seog
    • 한국경영과학회:학술대회논문집
    • /
    • 대한산업공학회/한국경영과학회 1996년도 춘계공동학술대회논문집; 공군사관학교, 청주; 26-27 Apr. 1996
    • /
    • pp.314-314
    • /
    • 1996
  • We investigate the scheduling problem for periodic job shops with blocking. We develop Petri net models for periodic job shops with finite buffers. A buffer control method would allow the jobs to enter the input buffer of the next machine in the order for which they are completed. We discuss difficulties in using such a random order buffer control method and random access buffers. We thus propose an alternative buffer control policy that restricts the jobs to enter the input buffer of the next machine in a predetermined order. The buffer control method simplifies job flows and control systems. Further, it requires only a cost-effective simple sequential buffer. We show that the periodic scheduling model with finite buffers using the buffer control policy can be transformed into an equivalent periodic scheduling model with no buffer, which is modeled as a timed marked graph. We characterize the structural properties for deadlock detection. Finally, we develop a mixed integer programming model for the no buffer problem that finds a deadlock-free optimal sequence that minimizes the cycle time.

  • PDF

Auto Regulated Data Provisioning Scheme with Adaptive Buffer Resilience Control on Federated Clouds

  • Kim, Byungsang
    • KSII Transactions on Internet and Information Systems (TIIS)
    • /
    • 제10권11호
    • /
    • pp.5271-5289
    • /
    • 2016
  • On large-scale data analysis platforms deployed on cloud infrastructures over the Internet, the instability of the data transfer time and the dynamics of the processing rate require a more sophisticated data distribution scheme which maximizes parallel efficiency by achieving the balanced load among participated computing elements and by eliminating the idle time of each computing element. In particular, under the constraints that have the real-time and limited data buffer (in-memory storage) are given, it needs more controllable mechanism to prevent both the overflow and the underflow of the finite buffer. In this paper, we propose an auto regulated data provisioning model based on receiver-driven data pull model. On this model, we provide a synchronized data replenishment mechanism that implicitly avoids the data buffer overflow as well as explicitly regulates the data buffer underflow by adequately adjusting the buffer resilience. To estimate the optimal size of buffer resilience, we exploits an adaptive buffer resilience control scheme that minimizes both data buffer space and idle time of the processing elements based on directly measured sample path analysis. The simulation results show that the proposed scheme provides allowable approximation compared to the numerical results. Also, it is suitably efficient to apply for such a dynamic environment that cannot postulate the stochastic characteristic for the data transfer time, the data processing rate, or even an environment where the fluctuation of the both is presented.

메모리 자원 사용 효율성 증진을 위한 적응적 네트워크 이중 버퍼 모델 (An Adaptive Network Double Buffer Model for Efficient Memory Resource Usage)

  • 최창범;이승룡
    • 한국정보과학회논문지:시스템및이론
    • /
    • 제33권11호
    • /
    • pp.810-819
    • /
    • 2006
  • 본 논문에서는 네트워크 통신에서 혼잡으로 인한 패킷의 손실을 최소화하기 위하여 새로운 버퍼 모델인 적응적인 이중 버퍼 모델을 제안한다. 이는 제약된 메모리 환경에서 송수신 버퍼가 서로의 여유 공간을 공유하여 패킷의 손실을 최대한 줄일 수 있는 버퍼 모델이다. 또한 리스트와 비슷한 성능을 지니는 본 버퍼 모델은 자유 리스트를 사용한 버퍼와 달리 메모리 누수로 인한 버블(bubbles) 현상을 방지하므로 제한된 환경의 네트워크 버퍼에 적용할 수 있으며 배열을 사용하는 경우와 비교 할 때 최대 100% 성능 향상을 기대할 수 있다.

연결기용 완충기의 시뮬레이션 모델 비교 (Comparison of Simulation Models for Train Buffer Couplings)

  • 장현목;김남욱;박영일
    • 한국자동차공학회논문집
    • /
    • 제18권4호
    • /
    • pp.107-114
    • /
    • 2010
  • Coupling systems for trains need more complicated buffer equipments than existing systems because the recent tendency of the regulations enforces trains to be safe for collisions even when the driving speed is higher than before. Using hydraulic buffer is an effective way to satisfy the requirement while it causes the increase of the cost for the coupling system. In this study, we introduce the methodology to build a simulation model for the hydraulic buffer, which could be installed into the coupling systems. In the simulation model of the hydraulic buffer, the reacting force is determined by both buffer stroke and speed whereas the elastic buffer model is designed by using only the buffer stroke in other studies. The simulation results with the advanced hydraulic buffer model shows that the simulating results can be close the real experimental results around 10%, and, if we considers friction forces, the simulation calculates the maximum force within 10% comparing to the experimental.

Cu/buffer layer/polyimide 시스템에서 Cr, 50%Cr-50%Ni 및 Ni 버퍼층에 따른 접착력 및 계면화학 (Adhesion Strength and Interface Chemistry with Cr, 50%Cr-50%Ni or Ni Buffer Layer in Cu/buffer Layer/polyimide System)

  • 김명한
    • 한국재료학회지
    • /
    • 제19권3호
    • /
    • pp.119-124
    • /
    • 2009
  • In the microelectronics packaging industry, the adhesion strength between Cu and polyimide and the thermal stability are very important factors, as they influence the performance and reliability of the device. The three different buffer layers of Cr, 50%Cr-50%Ni, and Ni were adopted in a Cu/buffer layer/polyimide system and compared in terms of their adhesion strength and thermal stability at a temperature of $300^{\circ}C$ for 24hrs. A 90-degree peel test and XPS analysis revealed that both the peel strength and thermal stability decreased in the order of the Cr, 50%Cr-50%Ni and Ni buffer layer. The XPS analysis revealed that Cu can diffuse through the thin Ni buffer layer ($200{\AA}$), resulting in a decrease in the adhesion strength when the Cu/buffer layer/polyimide multilayer is heat-treated at a temperature of $300^{\circ}C$ for 24hrs. In contrast, Cu did not diffuse through the Cr buffer layer under the same heat-treatment conditions.

Impact of playout buffer dynamics on the QoE of wireless adaptive HTTP progressive video

  • Xie, Guannan;Chen, Huifang;Yu, Fange;Xie, Lei
    • ETRI Journal
    • /
    • 제43권3호
    • /
    • pp.447-458
    • /
    • 2021
  • The quality of experience (QoE) of video streaming is degraded by playback interruptions, which can be mitigated by the playout buffers of end users. To analyze the impact of playout buffer dynamics on the QoE of wireless adaptive hypertext transfer protocol (HTTP) progressive video, we model the playout buffer as a G/D/1 queue with an arbitrary packet arrival rate and deterministic service time. Because all video packets within a block must be available in the playout buffer before that block is decoded, playback interruption can occur even when the playout buffer is non-empty. We analyze the queue length evolution of the playout buffer using diffusion approximation. Closed-form expressions for user-perceived video quality are derived in terms of the buffering delay, playback duration, and interruption probability for an infinite buffer size, the packet loss probability and re-buffering probability for a finite buffer size. Simulation results verify our theoretical analysis and reveal that the impact of playout buffer dynamics on QoE is content dependent, which can contribute to the design of QoE-driven wireless adaptive HTTP progressive video management.

하모니서치 알고리즘을 이용한 반도체 공정의 최적버퍼 크기 결정 (Determination of Optimal Buffer Size for Semiconductor Production System using Harmony Search Algorithm)

  • 이병길;변민석;김여진;이종환
    • 반도체디스플레이기술학회지
    • /
    • 제19권4호
    • /
    • pp.39-45
    • /
    • 2020
  • In the production process, the buffer acts as a buffer to alleviate some of the problems such as delays in delivery and process control failures in unexpected situations. Determining the optimal buffer size can contribute to system performance, such as increased output and resource utilization. However, there are difficulties in allocating the optimal buffer due to the complexity of the process or the increase in the number of variables. Therefore, the purpose of this research is proposing an optimal buffer allocation that maximizes throughput. First step is to design the production process to carry out the research. The second step is to maximize the throughput through the harmony search algorithm and to find the buffer capacity that minimizes the lead time. To verify the efficiency, comparing the ratio of the total increase in throughput to the total increase in buffer capacity.

Three Buffer 맥동관 냉동기에 관한 실험적 연구 (An Experimental Study of a Therr Buffer Pulse Tube Refrigerator)

  • 박성재;고득용;김효봉;신완순
    • 한국초전도ㆍ저온공학회논문지
    • /
    • 제1권2호
    • /
    • pp.54-59
    • /
    • 1999
  • An experimental study was carried out to improve the cooling capacity and performance of the pulse tube refrigerator. Three buffer pulse tube refrigerator was designed and fabricated, and the experimental apparatus operating process of the therr buffer pulse tube refrigerator and results obtained with the performance test. The cooldown characteristics and load characteristics are described. The lowest temperature measured in the three buffer pulse tube refrigerator was 88K and the cooling capacity at the optimum operating condition was 27 W at 120K.

  • PDF

최소 지연시간을 갖는 CMOS buffer 회로의 설계 기법 (the Design Methodology of Minimum-delay CMOS Buffer Circuits)

  • 강인엽;송민규;이병호;김원찬
    • 대한전자공학회논문지
    • /
    • 제25권5호
    • /
    • pp.509-521
    • /
    • 1988
  • In the designs of integrated circuits, the buffer circuits used for driving a large capacitive load from minimum-structured logic circuit outputs have important effects upon system throughputs. Therefore it is important to optimize the buffer circuits. In this paper, the principle of designing CMOS buffer circuits which have the minimum delay and drive the given capacitive load is discussed. That is, the effects of load capacitance upon rise time, fall time, and delay of the CMOS inverter and the effects of parasitic capacitances are finely analysed to calculate the requested minimum-delay CMOS buffer condition. This is different from the method by C.A. Mead et. al.[2.3.4.]which deals with passive-load-nMOS buffers. Large channel width MOS transistor stages are necessary to drive a large capacitive load. The effects of polysilicon gate resistances of such large stages upon delay are also analysed.And, the area of buffer circuits designed by the proposed method is smaller than that of buffer circuits designed by C.A. Mead's method.

  • PDF

버퍼 오버플로우 공격 방지를 위한 취약 함수 변환기 구현 (Implementation of a function translator converting vulnerable functions for preventing buffer overflow attacks)

  • 김익수;조용윤
    • 디지털산업정보학회논문지
    • /
    • 제6권1호
    • /
    • pp.105-114
    • /
    • 2010
  • C language is frequently used to develop application and system programs. However, programs using C language are vulnerable to buffer overflow attacks. To prevent buffer overflow, programmers have to check boundaries of buffer areas when they develop programs. But vulnerable programs frequently result from improper programming habits and mistakes of programmers. Existing researches for preventing buffer overflow attacks only inform programmers of warnings about vulnerabilities and not remove vulnerabilities in advance so that the programs still include vulnerabilities. In this paper, we propose a function translator which prevents creating programs including buffer overflow vulnerabilities. To prevent creating binary from source including vulnerabilities, the proposed translator searches vulnerable functions which cause buffer overflows, and converts them into secure functions. Accordingly, developing vulnerable programs by programmers which lack in knowledge on security can be prevented.