• Title/Summary/Keyword: Buffer(Memory)

Search Result 369, Processing Time 0.029 seconds

Call Admission Control for Shared Buffer Memory Switch Network with Self-Similar Traffic (Self-Similar 트래픽을 갖는 공유버퍼 메모리 스위치 네트워크 환경에서 호 수락 제어 방법)

  • Kim Ki wan;Kim Doo yong
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.30 no.4B
    • /
    • pp.162-169
    • /
    • 2005
  • Network traffic measurements show that the data traffic on packet switched networks has the self-similar features which is different from the traditional traffic models such as Poisson distribution or Markovian process model. Most of the call admission control researches have been done on the performance analysis of a single network switch. It is necessary to consider the performance analysis of the proposed admission control scheme under interconnected switch environment because the data traffic transmits through switches in networks. From the simulation results, it is shown that the call admission control scheme may not operate properly on the interconnected switch even though the scheme works well on a single switch. In this parer, we analyze the cell loss probability, utilization and self-similarity of output ports of the interconnected networks switch by using shared buffer memory management schemes and propose the new call admission control scheme considering the interconnected network switches under self-similar traffic environments.

Adaptive Garbage Collection Technique for Hybrid Flash Memory (하이브리드 플래시 메모리를 위한 적응적 가비지 컬렉션 기법)

  • Im, Soo-Jun;Shin, Dong-Kun
    • The KIPS Transactions:PartA
    • /
    • v.15A no.6
    • /
    • pp.335-344
    • /
    • 2008
  • We propose an adaptive garbage collection technique for hybrid flash memory which has both SLC and MLC. Since SLC area is fast and MLC area has low cost, the proposed scheme utilizes the SLC area as log buffer and the MLC area as data block. Considering the high write cost of MLC flash, the garbage collection for the SLC log buffer moves a page into the MLC data block only when the page is cold or the page migration invokes a small cost. The other pages are moved within the SLC log buffer. Also it adjusts the parameter values which determine the operation of garbage collection adaptively considering I/O pattern. From the experiments, we can know that the proposed scheme provides better performance compared with the previous flash management schemes for the hybrid flash and finds the parameter values of garbage collection close to the optimal values.

A JPEG Input Buffer Architecture for Real-Time Applications (실시간 JPEG 입력 버퍼 아키텍처)

  • Im, Min-Jung
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.39 no.2
    • /
    • pp.7-13
    • /
    • 2002
  • When a USB digital camera is used for PC video-conference applications, motion picture data need to be transferred to the PC through the USB port. Due to the mismatch between the data rates of the USB and the motion picture, data compression should be performed before the transmission from the USB. While many motion picture compression algorithms require large intermediate memory space, the JPEG algorithm does not need to store an entire frame for the compression. Instead, a relatively small buffer is required at the input of the JPEG compression engine to resolve the inconsistency between the orders of the inputted data and the consumed data. Data reordering can be easily implemented using a double buffering scheme, which still requires a considerable size of memory. In this paper, a novel memory management scheme is proposed to avoid the double buffering. The proposed memory architecture requires a small amount of memory and a simple address generation scheme, resulting in overall cost reduction.

The Architecture of the Frame Memory in MPEG-2 Video Encoder (MPEG-2 비디오 인코더의 프레임 메모리 구조)

  • Seo, Gi-Beom;Jeong, Jeong-Hwa
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.37 no.3
    • /
    • pp.55-61
    • /
    • 2000
  • This paper presents an efficient hardware architecture of frame memory interface in MPEG-2 video encoder. To reduce the size of memory buffers between SDRAM and the frame memory module, the number of clocks needed for each memory access is minimized with dual bank operation and burst length change. By allocating the remaining cycles not used by SDRAM access, to the random access cycle, the internal buffer size, the data bus width, and the size of the control logic can be minimized. The proposed architecture is operated with 54MHz clock and designed with the VT $I^{тм}$ 0.5 ${\mu}{\textrm}{m}$ CMOS TLM standard cell library. It is verified by comparing the test vectors generated by the c-code model with the simulation results of the synthesized circuit. The buffer area of the proposed architecture is reduced to 40 % of the existing architecture.

  • PDF

A Survey of the Index Schemes based on Flash Memory (NAND 플래쉬메모리 기반 색인에 관한 연구)

  • Kim, Dong-Hyun;Ban, Chae-Hoon
    • The Journal of the Korea institute of electronic communication sciences
    • /
    • v.8 no.10
    • /
    • pp.1529-1534
    • /
    • 2013
  • Since a NAND-flash memory is able to store mass data in a small sized chip and consumes low power, it is exploited on various hand-held devices, such as a smart phone and a sensor node, etc. To process efficiently mass data stored in the flash memory, it is required to use an index. However, since the write operation of the flash memory is slower than the read operation and an overwrite operation is not supported, the usage of existing index schemes degrades the performance of the index. In this paper, we survey the previous researches of index schemes for the flash memory and classify the researches by the methods to solve problems. We also present the performance factor to be considered when we design the index scheme on the flash memory.

A Buffer Cache Scheme Considering both DRAM/MRAM Hybrid Main Memory and Flash Memory Storages (DRAM/MRAM 하이브리드 메인 메모리와 플래시메모리 저장 장치를 고려한 버퍼 캐시 기법)

  • Yang, Soo-Hyun;Ryu, Yeon-Seung
    • Proceedings of the Korea Information Processing Society Conference
    • /
    • 2013.05a
    • /
    • pp.93-96
    • /
    • 2013
  • 모바일 환경에서 전력 손실이 중요한 문제 중 하나가 됨에 따라, MRAM과 플래시메모리와 같은 비 휘발성 메모리가 차세대 모바일 컴퓨터에 널리 사용될 것이다. 본 논문에서는 DRAM/MRAM 하이브리드 메인 메모리의 제한적인 쓰기 연산 성능을 고려한 효율적인 버퍼 캐시 기법을 연구했다. 제안한 기법은 MRAM 의 제한적인 쓰기 연산 성능을 고려하고 플래시 메모리 저장 장치의 삭제 연산 횟수를 최소화한다.

Adaptive Service Mode Conversion to Minimize Buffer Space Requirement in VOD Server (주문형 비디오 서버의 버퍼 최소화를 위한 가변적 서비스 모드 변환)

  • Won, Yu-Jip
    • Journal of KIISE:Computer Systems and Theory
    • /
    • v.28 no.5
    • /
    • pp.213-217
    • /
    • 2001
  • Excessive memory buffer requirement in continuous media playback is a serious impediment of wide spread usage of on-line multimedia service. Skewed access frequency of available video files provides an opportunity of re-using the date blocks which has been loaded by one session for later usage. We present novel algorithm which minimizes the buffer requirement in multiple sessions of multimedia playbacks. In continuous media playback originated from the disk, a certain amount of memory buffer is required to synchronize asynchronous disk. Read operation and synchronous playback operation. As aggregate playback bandwodth increases, larger amount of buffer needs to be allocated for this synchronization purpose. The focus of this work is to study the asymptotic behavior of the synchronization buffer requirement and to develop an algorithm coping with this excessive buffer requirement under bandwidth congestioon. We argue that in a large scale continuous media server, it may not be necessary to read the blocks for each session directly from the disk. The beauty of our work lies in the fact that it dynamically adapts to disk utilization of the server and finds the optimal way of servicinh the individual sessions while minimizing the overall buffer space requirement. Optimality of the proposed algorithm is shown by proof. The effectiveness and performance of the proposed scheme is examined via simulation.

  • PDF

Hot Carrier Induced Performance Degradation of Peripheral Circuits in Memory Devices (소자열화로 인한 기억소자 주변회로의 성능저하)

  • Yun, Byung-Oh;Yu, Jong-Gun;Jang, Byong-Kun;Park, Jong-Tae
    • Journal of the Korean Institute of Telematics and Electronics D
    • /
    • v.36D no.7
    • /
    • pp.34-41
    • /
    • 1999
  • In this paper, hot carrier induced performance degradation of peripheral circuits in memory devices such as static type imput buffer, latch type imput buffer and sense amplifier circuit has been measured and analyzed. The used design and fabrication of the peripheral circuits were $0.8 {\mu}m$ standard CMOS process. The analysis method is to find out which device is most significantly degraded in test circuits by using spice simulation, and then to characterize the correlation between device and circuit performance degradation. From the result of the performance degradation of static type input buffer, the trip point was increased due to the transconductance degradation of NMOS. In the case of latch type input buffer, there was a time delay due to the transconductance degradation of NMOS device. Finally, hot carrier induced the decrease of half-Vcc voltage and the increased of sensing voltage in sense amplifier circuits have been measured.

  • PDF

An Adaptive Buffer Tuning Mechanism for striped transport layer connection on multi-homed mobile host (멀티홈 모바일 호스트상에서 스트라이핑 전송계층 연결을 위한 적응형 버퍼튜닝기법)

  • Khan, Faraz-Idris;Huh, Eui-Nam
    • Journal of Internet Computing and Services
    • /
    • v.10 no.4
    • /
    • pp.199-211
    • /
    • 2009
  • Recent advancements in wireless networks have enabled support for mobile applications to transfer data over heterogeneous wireless paths in parallel using data striping technique [2]. Traditionally, high performance data transfer requires tuning of multiple TCP sockets, at sender's end, based on bandwidth delay product (BDP). Moreover, traditional techniques like Automatic TCP Buffer Tuning (ATBT), which balance memory and fulfill network demand, is designed for wired infrastructure assuming single flow on a single socket. Hence, in this paper we propose a buffer tuning technique at senders end designed to ensure high performance data transfer by striping data at transport layer across heterogeneous wireless paths. Our mechanism has the capability to become a resource management system for transport layer connections running on multi-homed mobile host supporting features for wireless link i.e. mobility, bandwidth fluctuations, link level losses. We show that our proposed mechanism performs better than ATBT, in efficiently utilizing memory and achieving aggregate throughput.

  • PDF

FRM: Foundation-policy Recommendation Model to Improve the Performance of NAND Flash Memory

  • Won Ho Lee;Jun-Hyeong Choi;Jong Wook Kwak
    • Journal of the Korea Society of Computer and Information
    • /
    • v.28 no.8
    • /
    • pp.1-10
    • /
    • 2023
  • Recently, NAND flash memories have replaced magnetic disks due to non-volatility, high capacity and high resistance, in various computer systems but it has disadvantages which are the limited lifespan and imbalanced operation latency. Therefore, many page replacement policies have been studied to overcome the disadvantages of NAND flash memories. Although it is clear that these policies reflect execution characteristics of various environments and applications, researches on the foundation-policy decision for disk buffer management are insufficient. Thus, in this paper, we propose a foundation-policy recommendation model, called FRM for effectively utilizing NAND flash memories. FRM proposes a suitable page replacement policy by classifying and analyzing characteristics of workloads through machine learning. As an implementation case, we introduce FRM with a disk buffer management policy and in experiment results, prediction accuracy and weighted average of FRM shows 92.85% and 88.97%, by training dataset and validation dataset for foundation disk buffer management policy, respectively.