• Title/Summary/Keyword: Blocking Voltage

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The NAND Type Flash EEPROM using the Scaled SCNOSFET (Scaled SONOSFET를 이용한 NAND형 Flash EEPROM)

  • Kim, Ju-Yeon;Kim, Byeong-Cheol;Kim, Seon-Ju;Seo, Gwang-Yeol
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.49 no.1
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    • pp.1-7
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    • 2000
  • The SNOSFET memory devices with ultrathin ONO(tunnel oxide-nitride-blocking oxide) gate dielectric were fabricated using n-well CMOS process and investigated its characteristics. The thicknesses of tunnel oxide, nitride and blocking oxide were $23{\AA},\; 53{\AA}\; and\; 33{\AA}$, respectively. Auger analysis shows that the ONO layer is made up of $SiO_2(upper layer of blocking oxide)/O-rich\; SiO_x\N\_y$. It clearly shows that the converting layer with $SiO_x\N\_y(lower layer of blocking oxide)/N-rich SiO_x\N\_y(nitride)/O-rich SiO_x\N\_y(tunnel oxide)$. It clearly shows that the converting layer with $SiO_x\N\_y$ phase exists near the interface between the blocking oxide and nitride. The programming condition of +8 V, 20 ms, -8 V, 50 ms is determined and data retention over 10 years is obtained. Under the condition of 8 V programming, it was confirmed that the modified Fowler-Nordheim tunneling id dominant charge transport mechanism. The programmed threshold voltage is distributed less than 0.1 V so that the reading error of memory stated can be minimized. An $8\times8$ NAND type flash EEPROM with SONOSFET memory cell was designed and simulated with the extracted SPICE parameters. The sufficient read cell current was obtained and the upper limit of $V_{TH}$ for write state was over 2V.

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Properties of Polymer Light Emitting Diodes Using PFO : MEH-PPV Emission Layer and Hole Blocking Layer (PFO : MEH-PPV 발광층과 정공 차단층을 이용한 고분자 발광다이오드의 특성)

  • Lee, Hak-Min;Gong, Su-Cheol;Shin, Sang-Bae;Park, Hyung-Ho;Jeon, Hyeong-Tag;Chang, Ho-Jung
    • Journal of the Semiconductor & Display Technology
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    • v.7 no.2
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    • pp.49-53
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    • 2008
  • The yellow base polymer light emitting diodes(PLEDs) with double emission and hole blocking layers were prepared to improve the light efficiency. ITO(indium tin oxide) and PEDOT : PSS[poly(3,4-ethylenedioxythiophene) : poly(styrene sulfolnate)] were used as cathode and hole transport materials. The PFO[poly(9,9-dioctylfluorene)] and MEH-PPV[poly(2-methoxy-5(2-ethylhe xoxy)-1,4-phenylenevinyle)] were used as the light emitting host and guest materials, respectively. TPBI[Tpbi1,3,5-tris(N-phenylbenzimidazol-2-yl)benzene] was used as hole blocking layer. To investigate the optimization of device structure, we prepared four kinds of PLED devices with different structures such as single emission layer(PFO : MEH-PPV), two double emission layer(PFO/PFO : MEH-PPV, PFO : MEH-PPV/PFO) and double emission layer with hole blocking layer(PFO/PFO : MEH-PPV/TPBI). The electrical and optical properties of prepared devices were compared. The prepared PLED showed yellow emission color with CIE color coordinates of x = 0.48, y = 0.48 at the applied voltage of 14V. The maximum luminance and current density were found to be about 3920 cd/$m^2$ and 130 mA/$cm^2$ at 14V, respectively for the PLED device with the structure of ITO/PEDOT : PSS/PFO/PFO : MEH-PPV/TPBI/LiF/Al.

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A Study on the Field Ring of High Voltage Characteristics Improve for the Power Semiconductor (전력반도체 고내압 특성 향상을 위한 필드링 최적화 연구)

  • Nam, Tae-Jin;Jung, Eun-Sik;Jung, Hun-Suk;Kim, Sung-Jong;Kang, Ey-Goo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.25 no.3
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    • pp.165-169
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    • 2012
  • Power semiconductor devices are widely used as high voltage applications to inverters and motor drivers, etc. The blocking voltage is one of the most important parameters for power semiconductor devices. And cause of junction curvature effects, the breakdown voltage of the device edge and device unit cells was found to be lower than the 'ideal' breakdown voltage limited by the semi-infinite junction profile. In this paper, Propose the methods for field ring design by DOE (Design of Experimentation). So The field ring can be improve for breakdown voltage and optimization.

DUAL DUTY CYCLE CONTROLLED SOFT-SWITCHING HIGH FREQUENCY INVERTER USING AUXILIARY REVERSE BLOCKING SWITCHED RESONANT CAPACITOR

  • Bishwajit, Saha;Suh, Ki-Young;Lee, Hyun-Woo;Mutsuo, Nakaoka
    • Proceedings of the KIEE Conference
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    • 2006.10d
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    • pp.129-131
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    • 2006
  • This paper presents a new ZVS-PWM high frequency inverter. The ZVS operation is achieved in the whole load range by using a simple auxiliary reverse blocking switch in parallel with series resonant capacitor. The operating principle and the operating characteristics of the new high frequency circuit treated here are illustrated and evaluated on the basis of simulation results. It was examined that the complete soft switching operation can be achieved even for low power setting ranges by introducing the high frequency dual duty cycle control scheme. In the proposed high frequency inverter treated here, the dual mode pulse modulation control strategy of the asymmetrical PWM in the higher power setting ranges and the lower power setting ones, the output power of this high frequency inverter could introduce in order to extend soft switching operation ranges. Dual duty cycle is used to provide a wide range of output power regulation that is important in many high frequency inverter applications. It is more suitable for induction heating applications the operation and control principle of the proposed high frequency inverter are described and verified through simulated results.

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Evaluation of a Three-Phase Three-Level ZVZCS DC-DC Converter Using Phase-Shift PWM Strategy

  • Kongwirat, Thammachat;Jangwanitlert, Anuwat
    • Journal of Electrical Engineering and Technology
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    • v.12 no.5
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    • pp.1902-1915
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    • 2017
  • This paper presents the evaluation of a three-phase three-level DC-DC converter which achieves the soft switching condition for all switches in the circuit and uses the phase-shift PWM strategy to adjust electric power at the output side. According to the analysis, the operation modes can be categorized into two cases: in the first case, where the phase shift angle is less than 120 degrees and in the second case, where the phase shift angle is more than 120 degrees. The outer switches of the circuit operate under ZVS condition and the inner switches operate under ZVZCS condition. It has been discovered that under ZCS condition of the inner switches, when the blocking capacitors decrease, they make the voltage across the blocking capacitor higher so the current reduce rapidly. A three-phase three-level DC-DC converter has a maximum efficiency of 93.5% when its load is of 5.7 kW. The results from the experiment have been compared to the results obtained by the $MATLAB^{(R)}$ simulator in order to confirm the validity of the proposed converter.

Protection of the MMCs of HVDC Transmission Systems against DC Short-Circuit Faults

  • Nguyen, Thanh Hai;Lee, Dong-Choon
    • Journal of Power Electronics
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    • v.17 no.1
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    • pp.242-252
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    • 2017
  • This paper deals with the blocking of DC-fault current during DC cable short-circuit conditions in HVDC (High-Voltage DC) transmission systems utilizing Modular Multilevel Converters (MMCs), where a new SubModule (SM) topology circuit for the MMC is proposed. In this SM circuit, an additional Insulated-Gate Bipolar Translator (IGBT) is required to be connected at the output terminal of a conventional SM with a half-bridge structure, hereafter referred to as HBSM, where the anti-parallel diodes of additional IGBTs are used to block current from the grid to the DC-link side. Compared with the existing MMCs based on full-bridge (FB) SMs, the hybrid topologies of HBSM and FBSM, and the clamp-double SMs, the proposed topology offers a lower cost and lower power loss while the fault current blocking capability in the DC short-circuit conditions is still provided. The effectiveness of the proposed topology has been validated by simulation results obtained from a 300-kV 300-MW HVDC transmission system and experimental results from a down-scaled HVDC system in the laboratory.

Floating Voltage Stacked LED Driver for Low Voltage Stress and Multi-channel Current Balancing (저 전압스트레스 및 다채널 전류 평형을 위한 Floating 전압 스택형 단일스위치 LED 구동회로)

  • Hwang, Won-Sun;Hwang, Sang-Soo;Kang, Jeong-Il;Han, Sang-Kyoo
    • The Transactions of the Korean Institute of Power Electronics
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    • v.20 no.2
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    • pp.122-129
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    • 2015
  • In this study, we propose a low voltage stress and cost-effective light emitting diode (LED) driver capable of multi-channel current balancing. Conventional LED drivers require as many boost converters as the number of LED channels, whereas the proposed LED driver requires only one buck converter and several balancing capacitors instead of several expensive boost converters. Additionally, while the components of the boost converter have high voltage stress and depend on the LED driving voltage, components of the proposed driver have about one-half of the voltage stress across all components. The proposed driver exhibits high reliability and cost effectiveness because it only uses few DC blocking capacitors with no additional active devices to balance the current of multi-channel LEDs. The proposed driver exhibits high reliability and cost effectiveness. The validity of the proposed driver is confirmed through a theoretical analysis. An explanation of the design considerations and experimental results were obtained using a prototype applicable to a 46" LED-TV.

Application of the H Infinity Control Principle to the Sodium Ion Selective Gating Channel on Biological Excitable Membranes

  • Hirayama, Hirohumi
    • International Journal of Control, Automation, and Systems
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    • v.2 no.1
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    • pp.23-38
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    • 2004
  • We proposed the infinity control principle to evaluate the Biological function. The H infinity control was applied to the Sodium (Na) ion selective gating channel on the excitable cellular membrane of the neural system. The channel opening, closing and inactivation processes were expressed by movements of three gates and one inactivation blocking particle in the channel pore. The rate constants of the channel state transition were set to be voltage dependent. The temporal changes in amounts per unit membrane area of the channel states were expressed by means of eight differential equations. The biochemical mimetic used to complete the Na ion selective channel was regarded as noise. The control inputs for ejecting the blocking particle with plugging in the channel pore were set for the active transition from inactivated states to a closed or open state. By applying the H infinity control, we computed temporal changes in the channel states, observers, control inputs and the worst case noises. The present paper will be available for evaluating the noise filtering function of the biological signal transmission system.

A Modified Current Differential Relay for Transformer Protection (변압기 보호용 수정 전류차동 계전방식)

  • 강용철;김은수;원성호
    • The Transactions of the Korean Institute of Electrical Engineers A
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    • v.53 no.2
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    • pp.80-86
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    • 2004
  • During magnetic inrush or over-excitation, saturation of the core in a transformer draws a large exciting current, which can cause mal-operation of a differential relay. This paper proposes a modified current differential relay for transformer protection. The relay calculates core-loss current from the induced voltage and the core-loss resistance; the relay calculates the magnetizing current from the core flux and the magnetization curve. Finally, the relay obtains the modified differential current by subtracting the core-loss and the magnetizing currents from the conventional differential current. Comparison study with the conventional differential relay with harmonic blocking is also shown. The proposed technique not only discriminates magnetic inrush and over-excitation from an internal fault, but also improves the speed of the conventional relay.

High Temperature Characteristics of SOI BMFET (SOI BMFET 의 고온 특성 분석)

  • Lim, Moo-Sup;Kim, Seoung-Dong;Han, Min-Koo;Choi, Yearn-Ik
    • Proceedings of the KIEE Conference
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    • 1996.07c
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    • pp.1579-1581
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    • 1996
  • The high temperature characteristics of SOI BMFET are analyzed by the numerical simulation and compared with MOS-gated SOI power devices at high temperatures. The proposed SOI BMFET combines bipolar operation in the on-state with unipolar FET operation in the off-state, so that it may be suitable for high temperature operation without any significant degradation of performance such as the leakage current and blocking capability. The simulation results show that SOI BMFET with a higher doped n-resurf layer is the most promising device far high temperature application as compared with MOS-gated SOI power devices, exhibiting the low on-state voltage drop as well as the excellent forward blocking capability at high temperature.

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