• 센서학회지
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• 제33권4호
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• pp.224-229
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• 2024

Quantum dot light-emitting diodes (QD-LEDs) are emerging as next-generation displays owing to their high color purity, wide color gamut, and solution processability. Enhancing the efficiency of QD-LEDs involves preventing non-radiative recombination mechanisms, such as Auger and interfacial recombination. Generally, ZnO serves as the electron transport layer, which is known for its higher mobility compared to that of organic semiconductors and can lead to excessive electron injection. Some of the injected electrons pass through the quantum dot emissive layer and undergo non-radiative recombination near or within the organic hole transport layer (HTL), resulting in HTL degradation. Therefore, the implementation of electron blocking layers (EBLs) is essential; however, studies on all-solution-processed inverted InP QD-LEDs are limited. In this study, poly(9-vinylcarbazole) (PVK) is introduced as an EBL to mitigate HTL degradation and enhance the emission efficiency of inverted InP QD-LEDs. Using a single-carrier device, PVK was confirmed to effectively inhibit electron overflow into the HTL, even at extremely low thicknesses. The optimization of the PVK thickness also ensured minimal disruption of the hole-injection properties. Consequently, a 1.5-fold increase in the maximum luminance was achieved in the all-solution-processed inverted InP QD-LEDs with the EBL.

• 한국정보과학회논문지:시스템및이론
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• 제36권6호
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• pp.463-475
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• 2009

플래시 메모리는 일관된 성능, 저전력 및 내구성 등의 특징으로 인해 실시간 시스템에 적합한 저장장치로 주목 받고 있다. 하지만 플래시 메모리는 무효화된 페이지의 가비지 컬렉션 수행을 위한 정체 시간(blocking time)을 필요로 하는데, 기존의 플래시 메모리 관리 기법에서는 가비지 컬렉션을 위한 최대 정체 시간(worst case blocking time)과 최소 정체 시간(best case blocking time)의 차가 크다는 문제점이 있다. 본 논문에서는 KAST라 불리는 FTL(Flash Translation Layer)을 제안하며, 제안 시스템에서 사용자는 가비지 컬렉션에 따른 최대 정체 시간을 설정할 수 있도록 한다. 실험을 통해 KAST는 사용자가 설정한 시간 내 가비지 컬렉션을 완료하며, 기존 FTL 보다 10~15% 성능 향상을 보임을 확인한다.

• 한국전기전자재료학회논문지
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• 제14권7호
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• pp.546-550
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• 2001

A new Lateral Trench Insulated Gate Bipolar Transistor(LTIGBT) with p$^{+}$ diverter was proposed to improve the characteristics of the conventional LTIGBT. The forward blocking voltage of the proposed LTIGBT with p$^{+}$ diverter was about 140V. That of the conventional LTIGBT of the same size was 105V. Because the p$^{+}$ diverter region of the proposed device was enclosed trench oxide layer, he electric field moved toward trench-oxide layer, and punch through breakdown of LTIGBT with p$^{+}$ diverter was occurred, lately. Therefore, the p$^{+}$ diverter of the proposed LTIGBT didn't relate to breakdown voltage in a different way the conventional LTIGBT. The Latch-up current densities of the conventional LTIGBT and proposed LTIGBT were 540A/$\textrm{cm}^2$, and 1453A/$\textrm{cm}^2$, respectively. The enhanced latch-up capability of the proposed LTIGBT was obtained through holes in the current directly reaching the cathode via the p$^{+}$ divert region and p$^{+}$ cathode layer beneath n$^{+}$ cathode layer./ cathode layer.

• Bulletin of the Korean Chemical Society
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• 제34권2호
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• pp.411-414
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• 2013

In order to enhance the photovoltaic property of the CdS/CdSe co-sensitized quantum dot sensitized solar cells (QDSSCs), the surface of nanoporous $TiO_2$ photoanode was modified by ultrathin $Al_2O_3$ layer before the deposition of quantum dots (QDs). The $Al_2O_3$ layer, dip-coated by 0.10 M Al precursor solution, exhibited the optimized performance in blocking the back-reaction of the photo-injected electrons from $TiO_2$ conduction band (CB) to polysulfide electrolyte. Transient photocurrent spectra revealed that the electron lifetime (${\tau}_e$) increased significantly by introducing the ultrathin $Al_2O_3$ layer on $TiO_2$ surface, whereas the electron diffusion coefficient ($D_e$) was not varied. As a result, the $V_{oc}$ increased from 0.487 to 0.545 V, without appreciable change in short circuit current ($J_{sc}$), thus inducing the enhancement of photovoltaic conversion efficiency (${\eta}$) from 3.01% to 3.38%.

• 전기학회논문지
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• 제61권1호
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• pp.85-88
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• 2012

DSCs are based on a dye-adsorbed porous $TiO_2$ layer as a photo electrode [1]. Under the illumination, dye molecules are excited and electrons are produced. The injected electrons in the conduction band of $TiO_2$ may recombine with the electrolyte. To obtain high performance DSCs, it is essential to retard the recombination. The charge recombination can be reduced by forming core-shell structure. In this work, we investigated the core-shell structure with $Al_2O_3$ and MgO coating layer on the porous $TiO_2$ layer. We confirmed the photovoltaic properties by I-V characteristics. The current and the efficiency was improved. In addition to, Through decrease in the width of EIS arc, which is the sum of the interfacial charge transfer resistances of both electrodes, we can be indicated that the block effect.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.260-260
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• 2016

최근 고화질 및 대용량 영상의 등장으로 메모리 디바이스에 대한 연구가 활발하다. 메모리 디바이스의 oxide 층은 tunnel layer, trap layer와 blocking layer로 나누어지며, tunnel layer와 trap layer 사이 계면의 상태는 메모리 특성에 큰 영향을 준다. 한편, AlOx는 메모리 디바이스의 tunnel layer에 주로 적용되는 물질로서, AlOx를 형성하는 방법에는 진공공정을 이용하여 증착하는 방법과 알루미늄을 산화시켜 형성하는 방법이 있다. 그 중, 진공공정 방법인 RF 스퍼터를 이용하는 방법은 증착시 sputtering으로 인하여 표면에 손상을 주게 되어, 산화시켜 형성한 AlOx에 비해 막질이 좋지 않다는 단점이 있다. 따라서 본 연구에서는 우수한 막질의 메모리 디바이스를 제작하기 위하여 산화시켜 형성한 AlOx를 tunnel layer로 적용시킨 MOSCAP을 제작하여 메모리 특성을 평가하였다. 제작된 소자는 n-Si (1-20 ohm-cm) 기판을 사용하였다. Tunnel layer는 e-beam evaporator를 이용하여 Al을 5 nm 두께로 증착하고 퍼니스를 이용하여 O2 분위기에서 $300^{\circ}C$의 온도로 1시간 동안 산화시켜 AlOx을 형성하였으며, 비교군으로 RF 스퍼터를 이용하여 AlOx를 10 nm 두께로 증착한 소자를 같이 제작하였다. 순차적으로, trap layer와 blocking layer는 RF 스퍼터를 이용하여 각각 HfOx 30 nm와 SiOx 30 nm를 증착하였다. 마지막으로 전극 물질로는 Al을 e-beam evaporator를 이용하여 150 nm 두께로 증착하였다. 제작된 소자에서 메모리 측정을 한 결과, 같은 크기의 윈도우를 비교하였을 때 산화시킨 AlOx를 tunnel layer로 적용한 MOSCAP에서 더 적은 전압으로도 program 동작이 나타나는 것을 확인하였다. 또한 내구성을 확인하기 위해 program/erase를 103회 반복하여 endurance를 측정한 결과, 스퍼터로 증착한 AlOx를 적용한 MOSCAP에서는 24 %의 메모리 윈도우 감소가 일어난 반면에, 산화시킨 AlOx를 적용한 MOSCAP에서는 메모리 윈도우 감소가 5 % 미만으로 일어났다. 결과적으로 산화시킨 AlOx를 메모리소자의 tunnel layer로 적용한 MOSCAP에서 더 뛰어난 내구성을 나타냈으며, 추후 최적의 oxide 두께와 열처리 조건을 통해 더 뛰어난 메모리 특성을 가지는 메모리 디바이스 제작이 가능할 것으로 기대된다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.388-388
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• 2012

In this letter, We have investigated cell characteristics of the alloy FePt-NDs charge trapping memory capacitors with high-k $Al_2O_3$ dielectrics as a blocking oxide. The capacitance versus voltage (C-V) curves obtained from a representative MOS capacitor embedded with FePt-NDs synthesized by the post deposition annealing (PDA) treatment process exhibit the window of flat-band voltage shift, which indicates the presence of charge storages in the FePt-NDs. It is shown that NDs memory with high-k $Al_2O_3$ as a blocking oxide has performance in large memory window and low leakage current when the diameter of ND is below 2 nm. Moreover, high-k $Al_2O_3$ as a blocking oxide increases the electric field across the tunnel oxide, while reducing the electric field across the blocking layer. From this result, this device can achieve lower P/E voltage and lower leakage current. As a result, a FePt-NDs device with high-k $Al_2O_3$ as a blocking oxide obtained a~7V reduction in the programming voltages with 7.8 V memory.

• Journal of Communications and Networks
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• 제6권3호
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• pp.269-279
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• 2004

A new online multi-layer integrated routing (MLIR) scheme that combines IP (electrical) layer routing with WDM (optical) layer routing is investigated. It is a highly efficient and cost-effective routing scheme viable for the next generation integrated optical Internet. A new simplified weighted graph model for the integrated optical Internet consisted of optical routers with multi-granularity optical-electrical hybrid switching capability is firstly proposed. Then, based on the proposed graph model, we develop an online integrated routing scheme called differentiated weighted fair algorithm (DWFA) employing adaptive admission control (routing) strategies with the motivation of service/bandwidth differentiation, which can jointly solve multi-layer routing problem by simply applying the minimal weighted path computation algorithm. The major objective of DWFA is fourfold: 1) Quality of service (QoS) routing for traffic requests with various priorities; 2) blocking fairness for traffic requests with various bandwidth granularities; 3) adaptive routing according to the policy parameters from service provider; 4) lower computational complexity. Simulation results show that DWFA performs better than traditional overlay routing schemes such as optical-first-routing (OFR) and electrical-first-routing (EFR), in terms of traffic blocking ratio, traffic blocking fairness, average traffic logical hop counts, and global network resource utilization. It has been proved that the DWFA is a simple, comprehensive, and practical scheme of integrated routing in optical Internet for service providers.

• 한국전기전자재료학회논문지
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• 제23권10호
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• pp.767-770
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• 2010

In this work, we investigated the static characteristics of 4H-SiC vertical metal-oxidesemiconductor field effect transistors (VMOSFETs) by adjusting the doping level of n-epilayer and the effect of a current spreading layer (CSL), which was inserted below the p-base region with highly doped n+ state ($5{\times}10^{17}cm^{-3}$). The structure of SiC VMOSFET was designed by using a 2-dimensional device simulator (ATLAS, Silvaco Inc.). By varying the n-epilayer doping concentration from $1{\times}10^{16}cm^{-3}$ to $1{\times}10^{17}cm^{-3}$, we investigated the static characteristics of SiC VMOSFETs such as blocking voltages and on-resistances. We found that CSL helps distribute the electron flow more uniformly, minimizing current crowding at the top of the drift region and reducing the drift layer resistance. For that reason, silicon carbide VMOSFET structures of highly intensified blocking voltages with good figures of merit can be achieved by adjusting CSL and doping level of n-epilayer.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.549-552
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• 2008

We have developed a novel bipolar host material with both electron and hole transporting characteristics. Since CGH(Cheil Green Host) has some electron transporting characteristics, it shows increased luminance efficiency in device including TCTA and without HBL(hole blocking layer:BAlq). Maximum power efficency of CGH was 27.4lm/W at the device structure ITO/DNTPD(60)/NPB(20)/TCTA(10)/EML(30)/Alq3(20)/LIF(1)/Al. We measured device performance again without HBL. The result of CGH showing 26.0lm/W is outstanding compared to that of CBP showing 19.1lm/W without holeblocking layer. We also measured lifetime and found to be 205hr at 3000nit, that is significant result compared to the life time of CBP device showing 82hr. CGH shows high device performance with holeblocking layer. Moreover, it shows better device performance and life time than those of CBP without holeblocking.