• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.12
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• pp.1792-1799
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• 1990

Two cases of block coded phase/frequncy modulations are investigated. minimum Euclidean distances are calculated as the function of modulation index h and rotation angle \ulcorner in the cases of 2-FSK/4-PSK and 2-FSK/8-PSK. Method of signal set partitioning is described, especially for the case of 2-FSK/8-PSK. The results are compared with S.I. Sayegh's work and shown better performance. For example, with simple parity check and repetition codes, we can get coding gain of 3 dB in the case of 2-FSK/4-PSK with block length n=4. We get 5.33 dB in the case of 2-FSK/8-PSK with n=4. And it is believed that we can get higher coding gain with proper combinations of block code and n-FSK/m-PSK type channel signal constellations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.8A
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• pp.814-821
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• 2002

The SPIHT(set partitioning in hierarchical tree) is efficient and well-known in the zerotree coding algorithm. However SPIHT's high memory requirement is a major difficulty for hardware implementation. In this paper we propose low-memory and fast zerotree algorithm. We present following three methods for reduced memory and fst coding speed. First, wavelet transform by lifting has a low memory requirement and reduced complexity than traditional filter bank implementation. The second method is to divide the wavelet coefficients into a block. Finally, we use NLS algorithm proposed by Wheeler and Pearlman in our codec. Performance of NLS is nearly same as SPIHT and reveals low and fixed memory and fast coding speed.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.1
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• pp.141-148
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• 2011

Most of the previous works on scene change detection algorithm focus on the detection of abrupt rather than gradual changes. In general, gradual scene change detection algorithms require heavy computation. Some of those approaches don't consider the error factors such as flashlights, camera or object movements, and special effects. Many scenes change detection algorithms based on the histogram show better performances than other approaches, but they have computation load problem. In this paper, we proposed a scene change detection algorithm with fast and accurate performance using the vertical and horizontal blocked slice images and their macro block informations. We apply graph cut partitioning algorithm for clustering and partitioning of video sequence using generated spatio-temporal histogram. When making spatio-temporal histogram, we only use the central block on vertical and horizontal direction for performance improvement. To detect camera and object movement as well as various special effects accurately, we utilize the motion vector and type information of the macro block.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.10 s.340
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• pp.25-30
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• 2005

This paper generalizes the concept of the signal space detection to construct a fixed delay tree search (FDTS) detector which estimates a block of n channel symbols at a time. This technique is applicable to high speed implementation. Two approaches are discussed both of which are based on efficient signal space partitioning. In the first approach, symbol detection is performed based on a multi-class partitioning of the signal space. This approach is a generalization of binary symbol detection based on a two-class pattern classification. In the second approach, binary signal detection is combined with a look-ahead technique, resulting in a highly parallel detector architecture.

• Journal of Broadcast Engineering
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• v.25 no.3
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• pp.338-345
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• 2020

Versatile Video Coding (VVC), which has been developing as a next generation video coding standard, has adopted various techniques to achieve more than twice the compression performance of HEVC (High Efficiency Video Coding). The recently released VVC Test Model (VTM) shows 38% Bjontegaard Delta bitrate (BD-rate) improvement and 9x/1.6x encoding/decoding complexity over HEVC. In order to reduce such increased complexity, various fast algorithms have been proposed. In this paper, gradient-based methods of fast intra mode decision and block splitting are presented. Experimental results show that, compared to VTM6.0, the proposed method gives up to 65% encoding time reduction with 3.54% BD-rate loss in All-Intra (AI) configuration.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.6
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• pp.62-69
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• 2015

In this paper, a new frame rate up conversion (FRUC) algorithm using adaptive motion estimation (AME-FRUC) is proposed. The proposed algorithm performs extended bilateral motion estimation (EBME) conducts motion estimation (ME) processes on the static region, and extract region of interest with the motion vector (MV). In the region of interest block, the proposed AME-FRUC uses the texture block partitioning scheme and the unilateral motion estimation for improving ME accuracy. Finally, motion compensated frame interpolation (MCFI) are adopted to interpolate the intermediate frame in which MCFI is employed adaptively based on ME scheme. Experimental results show that the proposed algorithm improves the PSNR up to 3dB, the SSIM up to 0.07 and 68% lower SAD calculations compared to the EBME and the conventional FRUC algorithms.

• ETRI Journal
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• v.22 no.1
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• pp.20-29
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• 2000

In this paper, we present a design of video and audio single chip encoder/decoder for portable multimedia application. The single-chip called as video audio signal processor (VASP) consists of a video signal processing block and an audio single processing block. This chip has mixed hardware/software architecture to combine performance and flexibility. We designed the chip by partitioning between video and audio block. The video signal processing block was designed to implement hardware solution of pixel input/output, full pixel motion estimation, half pixel motion estimation, discrete cosine transform, quantization, run length coding, host interface, and 16 bits RISC type internal controller. The audio signal processing block is implemented with software solution using a 16 bits fixed point DSP. This chip contains 142,300 gates, 22 Kbits FIFO, 107 kbits SRAM, and 556 kbits ROM, and the chip size is $9.02mm{\times}9.06mm$ which is fabricated using 0.5 micron 3-layer metal CMOS technology.

• Korean Journal of Remote Sensing
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• v.32 no.5
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• pp.471-482
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• 2016

This paper presents an extraction method for water body which uses block-based image partitioning and extension of water body boundaries to improve the performance of supervised classification for water body extraction. The Mahalanobis distance image is created by computing the spectral information of Normalized Difference Water Index (NDWI) and Near Infrared (NIR) band images over a training site within the water body in order to extract an initial water body area. To reduce the effect of noise contained in the Mahalanobis distance image, we apply mean curvature diffusion to the image, which controls diffusion coefficients based on connectivity strength between adjacent pixels and then extract the initial water body area. After partitioning the extracted water body image into the non-overlapping blocks of same size, we update the water body area using the information of water body belonging to water body boundaries. The update is performed repeatedly under the condition that the statistical distance between water body area belonging to water body boundaries and the training site is not greater than a threshold value. The accuracy assessment of the proposed algorithm was tested using KOMPSAT-2 images for the various block sizes between $11{\times}11$ and $19{\times}19$. The overall accuracy and Kappa coefficient of the algorithm varied from 99.47% to 99.53% and from 95.07% to 95.80%, respectively.

• Journal of Korea Multimedia Society
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• v.7 no.8
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• pp.1170-1182
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• 2004

A novel 4-way pipelined processing architecture is presented for three-step search block-matching motion estimation. For the 4-way pipelined processing, we have developed a method which divides the current block and search area into 4 subregions respectively and processes them concurrently. Also, we have developed memory partitioning method to access pixel data from 4 subregions concurrently without memory conflict. The architecture has been designed and simulated with C language and VHDL. Experimental results show that the proposed architecture achieves a high performance for real time motion estimation.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04b
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• pp.331-333
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• 2004

본 연구는 Haplotype 데이터에서 나타나는 별개의 Haplotype의 수를 최소화하는 블록으로 분할하는 방법을 제안한다. Multi-population case인 Haplotype 데이터를 분석하기 위해 패턴의 개수를 최소한으로 줄이는 볼록 분할 방법은 전산학적인 최적해의 의미를 가지게 되며, 이와 더불어 생물학적인 의미를 가지는 블록 경계를 찾기 위해 ｜D'｜ 을 계산하고 LD를 분석하였다 분석된 LD는 블록 분할 알고리즘에서 블록 결정 함수로 사용하였으며, 이에 대한 검정은 X$^2$-test를 통해 이루어졌다. 많은 Sample로 구성된 Haplotype 데이터로부터 평균 패턴의 개수를 최소화하고 긴 블록 길이를 가지는 블록 분할의 결과를 얻었다.