• Korean Journal of Computational Design and Engineering
• /
• v.17 no.6
• /
• pp.409-416
• /
• 2012

Most of the shipbuilding scheduling researches so far have been conducted with stress on the dock plan. That is due to the fact that the dock is the least extendable resource in shipyards and its overloading is difficult to resolve. However, once the dock scheduling is completed, it is also important to make a plan that make the best use of the rest of the resources in the shipyard, so that any additional cost is minimized. This study automates block allocation process by analyzing the existing manual process that designates production bays for the blocks during the midterm planning. Also, a planning scenario validation method is suggested, where block allocation scenarios based on diagrams are edited and simulated.

• IE interfaces
• /
• v.20 no.3
• /
• pp.395-406
• /
• 2007

In the telecommunication industry, estimation of the cost of network facilities is very important since depreciation cost of the facilities accounts for a large portion of the product cost. Moreover, cost estimation in the industry becomes more difficult because of increasing indirect cost upon digital convergence, expanding multi-purpose facilities, complexity of service product, etc. Nevertheless, not much seem to have been done in improving estimation methodology of the cost of network facilities. As a result, the quality of cost information on network facilities has deteriorated, and now even decision-makers in the industry dismiss the information. Recently, two major telecommunication companies adopted a new network cost estimation method to deal with the issue. In this paper, we study the concept of new cost estimation method and the procedure to develop and apply it. We also suggest the method to carry out the cost allocation using Matlab which is more efficient and time-saving than other commercial cost calculation packages.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.11 no.4
• /
• pp.309-317
• /
• 2011

This paper describes a baseband analog (BBA) chain for wireless local area network (WLAN) applications. For the given specifications of the receiver BBA chain, the optimum allocation of the gain and filter rejection of each block in a BBA chain is achieved to maximize the SFDR. The fully integrated BBA chain is fabricated in 0.13 ${\mu}m$ CMOS technology. An input-referred third-order intercept point (IIP3) of 22.9 dBm at a gain of 0.5 dB and an input-referred noise voltage (IRN) of 32.2 nV/${\surd}$Hz at a gain of 63.3 dB are obtained. By optimizing the allocation of the gain and filter rejection using the proposed design methodology, an excellent SFDR performance of 63.9 dB is achieved with a power consumption of 12 mW.

• International Journal of Naval Architecture and Ocean Engineering
• /
• v.6 no.1
• /
• pp.162-174
• /
• 2014

Most shipbuilding scheduling research so far has focused on the load level on the dock plan. This is because the dock is the least extendable resource in shipyards, and its overloading is difficult to resolve. However, once dock scheduling is completed, making a plan that makes the best use of the rest of the resources in the shipyard to minimize any additional cost is also important. Block assignment planning is one of the midterm planning tasks; it assigns a block to the facility (factory/shop or surface plate) that will actually manufacture the block according to the block characteristics and current situation of the facility. It is one of the most heavily loaded midterm planning tasks and is carried out manually by experienced workers. In this study, a method of representing the block assignment rules using a diagram was suggested through analysis of the existing manual process. A block allocation program was developed which automated the block assignment process according to the rules represented by the diagram. The planning scenario was validated through a case study that compared the manual assignment and two automated block assignment results.

• Journal of KIISE:Computer Systems and Theory
• /
• v.32 no.5
• /
• pp.232-242
• /
• 2005

This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in BFG represents a coarse grain block such as FIR and DCT and a port in a block may consume multiple data samples per invocation, which distinguishes our approach from behavioral synthesis and complicates the problem. In the presented design methodology, a dataflow graph with specified algorithm can be mapped to various hardware structures according to the resource allocation and schedule information. This simplifies the management of the area/performance tradeoff in hardware design and widens the design space of hardware implementation of a dataflow graph compared with the previous approaches. Through experiments with some examples, the usefulness of the proposed technique is demonstrated.