한국CDE학회논문집 (Korean Journal of Computational Design and Engineering)

  • 제17권6호
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  • Pages.409-416
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  • 2012
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  • 2508-4003(pISSN)
  • /
  • 2508-402X(eISSN)
한국CDE학회 (Society for Computational Design and Engineering)
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조선 중일정 블록 배량 계획 자동화 연구

An Automatic Block Allocation Methodology at Shipbuilding Midterm Scheduling

  • 황인혁 (서울대학교 조선해양공학과) ;
  • 남승훈 (서울대학교 조선해양공학과) ;
  • 신종계 (서울대학교 조선해양공학과)
  • Hwang, InHyuck (Department of Naval Architecture and Ocean Engineering, Seoul Nat'l University) ;
  • Nam, SeungHoon (Department of Naval Architecture and Ocean Engineering, Seoul Nat'l University) ;
  • Shin, JongGye (Department of Naval Architecture and Ocean Engineering, Seoul Nat'l University)
  • 투고 : 2012.03.12
  • 심사 : 2012.09.26
  • 발행 : 2012.12.01
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초록

Most of the shipbuilding scheduling researches so far have been conducted with stress on the dock plan. That is due to the fact that the dock is the least extendable resource in shipyards and its overloading is difficult to resolve. However, once the dock scheduling is completed, it is also important to make a plan that make the best use of the rest of the resources in the shipyard, so that any additional cost is minimized. This study automates block allocation process by analyzing the existing manual process that designates production bays for the blocks during the midterm planning. Also, a planning scenario validation method is suggested, where block allocation scenarios based on diagrams are edited and simulated.

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참고문헌

  1. Kim, H.H., Kang, J.H. and Park, S.S., 2002, Scheduling of Shipyard Block Assembly Process using Constraint Satisfaction Problem, Asia Pacific Management Review, 7(1), pp. 119-138.
  2. Kim, K.-D., Jeon, I.-W. and Kim, T.-H., 2002, A Study on Loading and Scheduling of Assembly Block in Shipbuilding, Journal of Industrial Technology, 22(B), pp. 61-70.
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  4. Lee, G.B. and Lee, J.S., 1999, The Application of a Virtual Plant Simulator and a Ladder Diagram of PLC, Proceedings of The Korean Institute of Electrical Engineers, No.7, pp. 699-702.
  5. Jee, E.K., Jeon, S.J. and Cha, S.D., 2009, A Formal Verification Technique for PLC Programs Implemented with Function Block Diagrams, Journal of KISS : Computing Practices, 15(3), pp. 211-215.
  6. Lee, S.-M., 2004, A Study on the Control Circuit Design of High Level Elevator Using SFC Language, M.SC Thesis, Changwon Univ.
  7. Lee, J.M., 2007, An Integrated Process and Evaluation Framework for Planning Production of Large Shipyards, Ph.D. Thesis, Seoul National Univ.