• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.1
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• pp.21-28
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• 2004

In this paper we apply block turbo coding at the transmitter and iterative decoding algorithm at the receiver for different operating modes, based on the 5 ㎓ IEEE 802.1 la WLAN system, instead of convolutional coding and soft decision viterbi algorithm to improve forward error correcting performance. Experimental results showed that each coding scheme outperforms coding gains of up to 3.5 ㏈ at the BER of 10$\^$-3/.

• The KIPS Transactions:PartC
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• v.8C no.3
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• pp.271-276
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• 2001

회의용 키분배 시스템은 회의용 키를 생성하여 키를 회의에 참석하고 있는 사람에게만 전달하여 서로간에 안전하게 통신하도록 한다. 본 논문에서는 Block Design의 한 분류인 symmetric balanced incomplete block design(SBIBD)를 적용한 효율적인 회의용 키분배시스템을 제안한다. 회의용 키를 생성하고 개인식별 정보를 근거로 하여 인증을 수행하는 통신 프로토콜이 설계된다. 제안된 프로토콜은 회의용 키를 생성하는 메시지의 복잡도를 최소화시키는데, SBIBD의 특별한 분류에서는 참석자의 수 v에 따라 메시지 복잡도는 O(v√v)가 된다. 보안시스템의 구현에서 중요한 요소인 프로토콜의 안전성은 factoring과 discrete logarithm을 계산할 정도로 난해하여 충분히 보장됨을 증명할 수 있다.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.3
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• pp.324-336
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• 2000

The paper proposes an efficient buffer management scheme to enhance performance of the disk I/O system. Without any user level information, the proposed scheme automatically detects the block reference patterns of applications by associating block attributes with forward distance of a block. Based on the detected patterns, the scheme applies an appropriate replacement policy to each application. We also present a new block allocation scheme to improve the performance of buffer cache when kernel needs to allocate a cache block due to a cache miss. The allocation scheme analyzes the cache hit ratio of each application based on block reference patterns and allocates a cache block to maximize cache hit ratios of system. These all procedures are performed on-line, as well as automatically at system level. We evaluate the scheme by trace-driven simulation. Experimental results show that our scheme leads to significant improvements in hit ratios of cache blocks compared to the traditional schemes and requires low overhead.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.1-8
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• 2009

We designed an ADC that operated upto 500Msamples/sec based on proposed R-string folding block as well as second folding block. The upper four bits are processed in parallel by the R-string folding block while the lower four bits are processed in pipeline structured second folding block to supply digital output. To verify the circuit performance, we conducted HSPICE simulation and the average power consumption was only 1.34mW even when the circuit was running at its maximum sampling frequency. We further measured noise immunity by applying linear ramp signal to the input. The DNL was between -0.56*LSB and 0.49*LSB and the INL was between -0.93*LSB and 0.72*LSB. We used 0.35 microns MOSIS device parameters for this work.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.6 no.2
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• pp.76-80
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• 2013

In this paper, a external electrode fluorescent lamp driving inverter for LCD backlight is designed. AC input from a lamp-driven system to process up to two inverter system for the existing configuration of power-efficient than the system as well as to increase the volume and weight reduction, Furthermore low-cost advantage. AC power input in order to drive EEFL stable and AC 85V ~ 265V power factor increase in the PFC Block can be used for running the Inverter Block EEFL and composed.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.153-156
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• 2002

FFT/IFFT block is very important module to determine the performance of OFDM system. This block has been implemented using several FFT algorithms such as radix-2, radix-4 etc. However SRFFT algorithm has not been implemented because of the complexity for implementation. This paper proposes a serial-pipeline SRFfT for OFDM system. The serial-pipeline SRFFT is optimized to use a serial input and serial output. We have implemented the SRFFT block using anam 0.25 Um five-metal process. The simulation show that the SRFFT block can operate about 200MHz. This architecture could be adapted to IEEE 802.lla wireless LAN standard.

• Journal of the Semiconductor & Display Technology
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• v.14 no.2
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• pp.67-72
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• 2015

For the development of UFS device test system, M-PHY specifications should be matched with MIPI-standard which is analog signal protocol. In this paper, the implementation methodology and hardware structure for the M-PHY AFE (Analog Front End) Block was suggested that it can be implemented using universal components without ASIC process. The testing procedure has a jitter problem so to solve the problems we using ASIC process, normally but the ASIC process needs a lot of developing cost making the UFS device test system. In is paper, the suggestion was verified by the output signal which was compared to the MIPI-standard on the Prototype-board using universal components. The board was reduced the jitter on the condition of HS-TX and 5.824 Gbps Mode in SerDes (Serialize-deserializer). Finally, the suggestion and developed AFE block have a useful better than ASIC process on developing costs of the industrial UFS device test system.

• Journal of information and communication convergence engineering
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• v.20 no.1
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• pp.1-7
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• 2022

Herein, a new space-time block coding technique is proposed for a MIMO 2 × 2 multiple-input multiple output (MIMO) system to minimize the bit error rate (BER) in Rayleigh fading channels with reduced decoding complexity using ZF and MMSE linear detection techniques. The main objective is to improve the service quality of wireless communication systems and optimize the number of antennas used in base stations and terminals. The idea is to exploit the correlation product technique between both information symbols to transmit per space-time block code and their own orthogonal Walsh-Hadamard sequences to ensure orthogonality between both symbol vectors and create a full-rate orthogonal STBC code. Using 16 quadrature amplitude modulation and the quasi-static Rayleigh channel model in the MATLAB environment, the simulation results show that the proposed space-time block code performs better than the Alamouti code in terms of BER performance in the 2 × 2 MIMO system for both cases of linear decoding ZF and MMSE.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.64-68
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• 2004

Design of manufacturing system is a very complicated and tricky process. Since no efficient method has been known, yet it has been mainly done based on experience and heuristics. Even mostly used simulation approaches can only evaluate the performance of an already configured system, but cannot provide a help to configure or reconfigure a manufacturing system. An efficient way to (re-)configure manufacturing systems might be to use building blocks of a manufacturing system in the similar manner the recent products are configured based on modular principle. In this paper, the concept of a building block and its representation method are described. An example of assembly system configuration is also given.

• Journal of Ocean Engineering and Technology
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• v.21 no.2 s.75
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• pp.81-86
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• 2007

This paper presents a computer aided process planning system integrating case-based reasoning and expert system for block assembly in shipbuilding. Expert rules are extracted from the case-base where cases are represented as a set of constraint-satisfaction problems. Rules for the expert system are extracted by generalizing the constraints. In generalizing the constraints, parts are generalized as variables or as part-types. The system was developed with CLIPS, an expert system shell. As more cases are collected, more rules will be extracted and the existing rules will be updated.