• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.59-62
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• 2000

As the density of memories increases, unwanted interference between cells and coupling noise between bit-lines are increased and testing high density memories for a high degree of fault coverage can require either a relatively large number of test vectors or a significant amount of additional test circuitry. From now on, conventional test algorithms have focused on faults between neighborhood cells, not neighborhood bit-lines. In this paper, a new algorithm for NPSFs, and neighborhood bit-line sensitive faults (NBLSFs) based on the NPSFs are proposed. Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a three-cell layout which is minimum size for NBLSFs detection is used. To consider faults by maximum coupling noise by neighborhood bit-lines, we added refresh operation after write operation in the test procedure(i.e., write \longrightarrow refresh \longrightarrow read). Also, we present properties of the algorithm, such as its capability to detect stuck-at faults, transition faults, conventional pattern sensitive faults, and neighborhood bit-line sensitive faults.

• Journal of Korea Society of Digital Industry and Information Management
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• v.4 no.4
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• pp.9-19
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• 2008

In this paper, it is studied anti-collision algorithm based on the transmission protocol for RFID baseband system of the lSO/IEC 18000-6 Type-C regulation and designed the baseband part of RFID reader system using FPGA. To compensate this weak point of the slot random aloha algorithm which must have a long time to be dumped before deciding an appropriate slot size according to the number of surrounding tag, we suggested how to apply Bit By Bit algorithm to be able to recognize the tag when the tag is clashing. The design of the baseband part in the RFID reader system is accomplish by use of the ISE9.1i and I made an experiment on it targeting Spartan2. Construction verification is measured each block through Logic Analyzer and I can verify it has no error. I also compared and analyzed the performance between proposed algorithm and past algorithm and verified the improvement of performance.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.2
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• pp.18-26
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• 2009

When channel state information (CSI) is available at the transmitter, the system throughput can be enhanced by adaptive transmissions and opportunistic multiuser scheduling. In this paper, we consider multiple-input multiple-output (MIMO) systems employing bit-interleaved coded orthogonal frequency division multiplexing (BIC-OFDM). We first propose a bit-loading algorithm based on the Levin-Campello algorithm for the BIC-OFDM. Then we will apply this algorithm to the MIMO system with a finite set of constellations, by reassigning residual power on each stream Simulation results show that proposed bit-loading scheme which takes the residual power into account improves the system performance especially at high signal-to-noise ratio (SNR) range.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.565-571
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• 2010

This paper proposes a parity discrimination algorithm which discriminates N bit parity using a perceptron neural network and back propagation algorithm. This algorithm decides minimum hidden unit numbers when discriminates N bit parity. Therefore, this paper implements parity discrimination experiments for N bit by changing hidden unit numbers of the proposed perceptron neural network. Experiments confirm that the proposed algorithm is possible to discriminates N bit parity.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.05a
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• pp.795-798
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• 2007

RFID 리더기가 영역내의 다수의 태그를 인식하기 위해선 충돌방지 알고리즘이 필수적으로 요구된다. 본 논문은 Auto ID Class 0에서 정의한 충돌방지 알고리즘인 Bit-by-Bit 이진트리 알고리즘(BBB)의 충돌 위치를 스택에 저장하고 이를 통해 다음 질의어를 결정함으로써 성능이 크게 개선된 Stack-bit-by-bit(SBBB) 알고리즘을 제안한다. 시뮬레이션을 통한 검증결과 질의-응답 횟수, 질의어의 크기, 응답어의 크기의 모든 면에서 성능이 개선된 것을 확인할 수 있었다.

• Journal of Korea Multimedia Society
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• v.3 no.4
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• pp.372-379
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• 2000

In this paper, we propose a fast variable-size block matching algorithm for motion estimation based on bit-pattern. Motion estimation in the proposed algorithm is performed after the representation of image sequence is transformed 8bit pixel values into 1bit ones depending on the mean value of search block, which brings a short searching time by reducing the computational complexity. Moreover, adaptive searching methods according to the motion information of the block make the procedure of motion estimation efficient by eliminating an unnecessary searching of low motion block and deepening a searching procedure in high motion block. Experimental results show that the proposed algorithm provides better performance-0.5dB PSNR improvement-than full search block matching algorithm with a fixed block size.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.7
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• pp.3455-3474
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• 2018

As a unique form of signed-digit representation, non-adjacent form (NAF) minimizes Hamming weight by removing a stream of non-zero bits from the binary representation of positive integer. Thanks to this strong point, NAF has been used in various applications such as cryptography, packet filtering and so on. In this paper, to improve the NAF conversion speed of the $NAF_w$ algorithm, we propose a new NAF conversion algorithm, called w-bit Shifting Non-Adjacent Form($SNAF_w$), where w is width of scanning window. By skipping some unnecessary bit comparisons, the proposed algorithm improves the NAF conversion speed of the $NAF_w$ algorithm. To verify the excellence of the $SNAF_w$ algorithm, the $NAF_w$ algorithm and the $SNAF_w$ algorithm are implemented in the 8-bit microprocessor ATmega128. By measuring CPU cycle counter for the NAF conversion under various input patterns, we show that the $SNAF_2$ algorithm not only increases the NAF conversion speed by 24% on average but also reduces deviation in the NAF conversion time for each input pattern by 36%, compared to the $NAF_2$ algorithm. In addition, we show that $SNAF_w$ algorithm is always faster than $NAF_w$ algorithm, regardless of the size of w.

• The KIPS Transactions:PartA
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• v.18A no.6
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• pp.265-270
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• 2011

Even though 32-bit ISA based microprocessors are widely used more and more, 16-bit ISA based processors are still being frequently employed for embedded systems. Intel 8086, 80286, Motorola 68000, and ADChips AE32000 are the representatives of the 16-bit ISA based processors. However, due to less expressiveness of the 16-bit ISA from its narrow bit width, we need to execute more 16-bit instructions for the same implementation compared to 32-bit instructions. Because the number of executed instructions is a very important factor in performance, we have to resolve the problem by improving the expressiveness of the 16-bit ISA. In this paper, we propose a new pair register allocation algorithm to enhance an original graph-coloring based register allocation algorithm. Also, we explain about both the performance result and further research directions.

• ETRI Journal
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• v.29 no.4
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• pp.445-451
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• 2007

An adaptive modulation scheme is presented for multiuser orthogonal frequency-division multiplexing systems. The aim of the scheme is to minimize the total transmit power with a constraint on the transmission rate for users, assuming knowledge of the instantaneous channel gains for all users using a combined bit-loading and subcarrier allocation algorithm. The subcarrier allocation algorithm identifies the appropriate assignment of subcarriers to the users, while the bit-loading algorithm determines the number of bits given to each subcarrier. The proposed bit-loading algorithm is derived from the geometric progression of the additional transmission power required by the subcarriers and the arithmetic-geometric means inequality. This algorithm has a simple procedure and low computational complexity. A heuristic approach is also used for the subcarrier allocation algorithm, providing a trade-off between complexity and performance. Numerical results demonstrate that the proposed algorithms provide comparable performance with existing algorithms with low computational cost.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1997.06a
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• pp.31-36
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• 1997

Bit allocation is a critical problem in video encoding such as MPEG. To improve the quality of the reconstructed sequence for a given bit rate, the assigned target bits for a group of pictures (GOP) must be allocated to each picture efficiently. In this paper, we derive a target bit allocation algorithm for more efficient rate control, by assuming that the average rate-distortion curve for an input source is logarithmic. This target bit allocation is based on Shannon's rate-distortion theory, which deals with the minimization of source distortion subject to a channel rate constraint. Simulation results show that the proposed target bit allocation algorithm provides better performance than the one in MPEG-2 Test Model 5 (TM5).