• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.557-565
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• 2005

This paper presents the development and implementation of a zero-copy file transfer mechanism that improves the efficiency of file transfers for PC cluster systems using hardware-based VIA(Virtual Interface Architecture) network adapters. VIA is one of the representative user-level communication interfaces, but because there is no library for file transfer, one copy occurs between kernel buffer and user boilers. Our mechanism presents a file transfer primitive that does not require the file system to be modified and allows the NIC to transfer data from the kernel buffer to the remote node directly without copying. To do this, we have developed a hardware-based VIA network adapter, which supports the PCI 64bit/66MHz bus and Gigabit Ethernet, as a NIC, and implemented a zero-copy file transfer mechanism. The experimental results show that the overhead of data coy and context switching in the sender is greatly reduced and the CPU utilization of the sender is reduced to $30\%\~40\%$ of the VIA send/receive mechanism. We demonstrate the performance of the zero-copy file transfer mechanism experimentally. and compare the results with those from existing file transfer mechanisms.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.49 no.2
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• pp.94-101
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• 2012

This paper proposes an improved image steganalysis scheme to raise the detection rate of stego images out of cover images. To improve the detection rate of stego image in the steganalysis, tiny variation caused by data hiding should be amplified. For this, we extract feature vectors of cover image and stego image by two steps. First, we separate image into upper 4 bit subimage and lower 4 bit subimage. As a result, stego noise is expanded more than two times. We decompose separated subimages into twelve subbands by applying 3-level Haar wavelet transform and calculate co-occurrence probabilities of two different subbands in the same scale. Since co-occurrence probability of the two wavelet subbands is affected by data hiding, it can be used as a feature to differentiate cover images and stego images. The extracted feature vectors are used as the input to the multilayer perceptron(MLP) classifier to distinguish between cover and stego images. We test the performance of the proposed scheme over various embedding rates by the LSB, S-tool, COX's SS, and F5 embedding method. The proposed scheme outperforms the previous schemes in detection rate to existence of hidden message as well as exactness of discrimination.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.4
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• pp.58-66
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• 2009

Recently the emerging demands of the light-video encoder promotes lots of research efforts on DVC (Distributed Video Coding). As an appropriate video compression method, DVC has been studied, and Wyner-Ziv (WZ) video compression is its one representative structure. The WZ encoder splits the image into two kinds of frames, one is key frame which is compressed by conventional intra coding, and the other is WZ frame which is encoded by WZ coding. The WZ decoder decodes the key frame first, and estimates the WZ frame using temporal correlation between key frames. Estimated WZ frame (Side Information) cannot be the same as the original WZ frame due to the absence of the WZ frame information at decoder. As a result, the difference between the estimated and original WZ frames are regarded as virtual channel noise. The WZ frame is reconstructed by removing noise in side information. Therefore precise noise estimation produces good performance gain in WZ video compression by improving error correcting capability by channel code. But noise cannot be estimated precisely at WZ decoder unless there is good WZ frame information, and generally it is estimated from the difference of corresponding key frames. Also the estimated noise is limited by comparing with frame level noise to reduce the uncertainty of the estimation method. However these methods cannot provide good noise estimation for every frame or each bit plane. In this paper, we propose a noise nodel selection method which chooses a better noise model for each bit plane after generating candidate noise models. Experimental result shows PSNR gain up to 0.8 dB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1107-1114
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• 2004

System Packet Interface Level 4 Phase 2(SPI-4.2) is an interface for packet and cell transfer between a physical layer(PHY) device and a link layer device, for aggregate bandwidths of OC-192 ATM and Packet Over Sonet/SDH(POS), as well as 10Gbps Ethernet applications. SPI-4.2 core consists of Tx and Rx modules and supports full duplex communication. Tx module of SPI-4.2 core writes 64-bit data word and 14-bit header information from the user interface into asynchronous FIFO and transmits DDR(Double Data Rate) data over PL4 interface. Rx module of SPI-4.2 core operates in vice versa. Tx and Rx modules of SPI-4.2 core are designed to support maximum 256-channel and control the bandwidth allocation by configuring the calendar memory. Automatic DIP4 and DIP-2 parity generation and checking are implemented within the designed core. The designed core uses Xilinx ISE 5.li tool and is described in VHDL Language and is simulated by Model_SIM 5.6a. The designed core operates at 720Mbps data rate per line, which provides an aggregate bandwidth of 11.52Gbps. SPI-4.2 interface core is suited for line cards in gigabit/terabit routers, and optical cross-connect switches, and SONET/SDH-based transmission systems.

• Journal of the Korea Society of Computer and Information
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• v.12 no.5
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• pp.103-112
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• 2007

In this paper, we implement a hypervisor that runs multiple uC/OS-II real-time kernels on one microprocessor. The hypervisor virtualizes microprocessor and memory that are main resources managed by uC/OS-II kernel. Microprocessor is virtualized by controlling interrupts that uC/OS-II real-time kernel handles and memory is virtualized by partitioning physical memory. The hypervisor consists of three components: interrupt control routines that virtualize timer interrupt and software interrupt, a startup code that initializes the hypervisor and uC/OS-II kernels, and an API that provides communication between two kernels. The original uC/OS-II kernel needs to be modified slightly in source-code level to run on the hypervisor. We performed a real-time test and an independent computation test on Jupiter 32-bit EISC microprocessor and showed that the virtualized kernels run without problem. The result of our research can reduce the hardware cost, the system space and weight, and system power consumption when the hypervisor is applied in embedded applications that require many embedded microprocessors.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.26-36
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• 2014

The needs of active phased arrays antenna system is getting more increased for IMT-Advanced system efficiency. The active phased array structure consists of lots of small transceivers and radiation elements to increase system efficiency. The minimized module of high efficiency transceiver is key for system implementation. The power amplifier of transmitter decides efficiency of base-station. In this paper, we design and implement minimized module of high efficiency transceiver for IMT-Advanced active phased array system. The temperature compensation circuit of transceiver reduces gain error and the analog pre-distorter of linearizer reduces implemented size. For minimal size and high efficiency, the implented power amplifier consist of GaN MMIC Doherty structure. The size of implemented module is $40mm{\times}90mm{\times}50mm$ and output power is 47.65 dBm at LTE band 7. The efficiency of power amplifier is 40.7% efficiency and ACLR compensation of linearizer is above 12dB at operating power level, 37dBm. The noise figure of transceiver is under 1.28 dB and amplitude error and phase error on 6 bit control is 0.38 dB and 2.77 degree respectively.

• Journal of IKEEE
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• v.14 no.2
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• pp.51-57
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• 2010

A CMOS rail-to-rail high voltage buffer amplifier is proposed to drive the gamma correction reference voltage of large TFT LCD panels. It is operating by a single supply and only shows current consumption of 0.5mA at 18V power supply voltage. The circuit is designed to drive the gamma correction voltage of 8-bit or 10-bit high resolution TFT LCD panels. The buffer has high slew rate, 0.5mA static current and 1k$\Omega$ resistive and capacitive load driving capability. Also, it offers wide supply range, offset voltages below 50mV at 5mA constant output current, and below 2.5mV input referred offset voltage. To achieve wide-swing input and output dynamic range, current mirrored n-channel differential amplifier, p-channel differential amplifier, a class-AB push-pull output stage and a input level detector using hysteresis comparator are applied. The proposed circuit is realized in a high voltage 0.18um 18V CMOS process technology for display driver IC. The circuit operates at supply voltages from 8V to 18V.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.5_6
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• pp.371-378
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• 2004

This paper presents the implementation and performance of the HVIA-GE card, which is a hardware implementation of the Virtual Interface Architecture (VIA) based on Gigabit Ethernet. The HVIA-GE card is a 32-bit/33MHz PCI adapter containing an FPGA for the VIA protocol engine and a Gigabit Ethernet chip set to construct a high performance physical network. HVIA-GE performs virtual-to-physical address translation, Doorbell, and send/receive completion operations in hardware without kernel intervention. In particular, the Address Translation Table (ATT) is stored on the local memory of the HVIA-GE card, and the VIA protocol engine efficiently controls the address translation process by directly accessing the ATT. As a result, the communication overhead during send/receive transactions is greatly reduced. Our experimental results show the maximum bandwidth of 93.7MB/s and the minimum latency of 11.9${\mu}\textrm{s}$. In terms of minimum latency HVIA-GE performs 4.8 times and 9.9 times faster than M-VIA and TCP/IP, respectively, over Gigabit Ethernet. In addition, the maximum bandwidth of HVIA-GE is 50.4% and 65% higher than M-VIA and TCP/IP respectively.

• Journal of Korean Philosophical Society
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• v.148
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• pp.29-47
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• 2018

The relationship between Confucian tradition and modern China has been discussed since the last century only on a preconceived level of "pre-modernization" without practical orientation, since the discussion has been referred to the modern West while China has not yet commenced modernization. Such being the case, it is of great significance to revert to this topic in the contemporary context of China's modernization. In other words, such new discussions are concerned with a series of difficulties China is presently confronted. To put it brief, the profit-oriented market economy has bit by bit undermined the traditional customs of the mild agricultural society, resulting in the emotional apathy among people, crush of the ethical order, discard of morality in life, ignorance of man's spiritual existence, and ultimately the extremely unbalanced development of "beggar-thy-neighbor" situation among ethnic groups, countries and regions. Since Confucius time, the Confucian tradition has always been attaching great importance to purify customs through social rules for etiquette and harmony, in the process of which, the ethic order is arranged to promote the emotional communication among group members, the individuals are cultivated to enhance their spiritual realms, and most importantly, those social rules for etiquette and harmony are casted as forms of civilization so as to achieve peace and harmony of the whole world. The integration of these three aspects of the Confucian tradition can undoubtedly provide a reference for solving considerable problems confronted by modern China.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.5
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• pp.329-337
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• 2001

It has been known that the leakage current in the low field region consists of the dielectric relaxation current and intrinsic leakage current, which cause the charge loss in dynamic random access memory (DRAM) storage capacitor using (Ba,Sr)TiO$_{3}$ (BST) thin film. Especially, the dielectric relaxation current should be seriously considered since its magnitude is much larger than that of the intrinsic leakage current in giga-bit DRAM operation voltage (~IY). In this study, thermally stimulated current (TSC) measurement was at first applied to investigate the activation energy of traps and relative evaluation of the density of traps according to process change. And, through comparing TSC to early methods of I-V or I-t measurement and analyzing, we identify the origin of the dielectric relaxation current and investigate the reliability of TSC measurement. First, the polarization condition such as electric field, time, temperature and heating rate was investigated for reliable TSC measurement. From the TSC measurement, the energy level of traps in the BST thin film has been investigated and evaluated to be 0.20($\pm$0.01) eV and 0.45($\pm$0.02) eV. Based on the TSC measurement results before and after rapid thermal annealing (RTA) process, oxygen vacancy is concluded to be the origin of the traps. TSC characteristics with thermal annealing in the MIM BST capacitor have shown the same trends with the current-voltage (I-V) and current-time (I-t) characteristics. This means that the TSC measurement is one of the effective methods to characterize the traps in the BST thin film.