• Journal of Broadcast Engineering
• /
• v.22 no.2
• /
• pp.193-206
• /
• 2017

In this paper, we propose a rate control method based on the $R-{\lambda}$ model that supports a parallel encoding structure in GOP levels or IDR period levels for 4K UHD input video in real-time. For this, a slice-level bit allocation method is proposed for parallel encoding instead of sequential encoding. When a rate control algorithm is applied in the GOP level or IDR period level parallelism, the information of how many bits are consumed cannot be shared among the frames belonging to a same frame level except the lowest frame level of the hierarchical B structure. Therefore, it is impossible to manage the bit budget with the existing bit allocation method. In order to solve this problem, we improve the bit allocation procedure of the conventional ones that allocate target bits sequentially according to the encoding order. That is, the proposed bit allocation strategy is to assign the target bits in GOPs first, then to distribute the assigned target bits from the lowest depth level to the highest depth level of the HEVC hierarchical B structure within each GOP. In addition, we proposed a processing method that is used to improve subjective image qualities by allocating the bits according to the coding complexities of the frames. Experimental results show that the proposed bit allocation method works well for frame-level parallel HEVC software encoders and it is confirmed that the performance of our rate controller can be improved with a more elaborate bit allocation strategy by using the preprocessing results.

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.325-328
• /
• 2002

In this paper, we present a SystemC model of a 32-Bit RISC core wi)ich is based on the ARMTTDMI architecture. The RISC core model was first modeled in C for architecture verification and then refined down to a level that allows concurrent behavior lot hardware timing using the SystcmC class library. It was driven in timed functional level that uses handshake protocol. It was compiled using standard C++ compiler. The functional simulation result was verified by comparing the contents of memory, the result of execution with the result from the ARMulator of ADS(Arm Developer Suite).

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.416-420
• /
• 1999

This paper describes a 32-bit RISC processor, which has instruction level compatibility with the ARM7 microprocessor. The processor is fully synthesizable, and its performance is evaluated based on 0.35-${\mu}{\textrm}{m}$ CMOS library. This paper focuses on the implementation of the processor and the reliable verification strategy ensuring the complete instruction level compatibility. The processor has successfully verified using a FPGA chip.

• Journal of Korean Society of Industrial and Systems Engineering
• /
• v.10 no.16
• /
• pp.81-88
• /
• 1987

This article develops to determine and to allocate the two level factors at the table of orthogonal arrays. The column numbers of two factors and two-factor interaction can be determined in applying the bit-by-bit EX-OR operation. The assignment of the Two factors and Two factor interaction is attained by USING COMPUTER, IBM PC/AT applying algorithm of EX-OR operation Theory.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.40 no.9
• /
• pp.1667-1671
• /
• 2015

Multi-level holographic data storage is a candidate for the next generation data storage system, since it can store more than one bit per pixel. It is possible to increase the number of codewords if the number of levels is increased, and the code with an appropriate selection of codewords can also increase the minimum distance. In this paper, we propose three multi-level modulation codes of the code rate 1 bit/pixel and compare the performance according to the minimum distance. The result shows that the code with small number of levels is better than that of large number of levels because it is hard to detect threshold value.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.44 no.8
• /
• pp.17-22
• /
• 2007

In this paper, we propose a threshold estimation algorithm for a noncoherent IR-UWB receiver using 1-bit sampler. The proposed method reduces the hardware complexity by using the information of binary data resulted from 1-bit sampler instead of measuring the energy level of a received signal. Besides, mathematical modeling shows that the performances are similar to those of theoretically optimal threshold in terms of bit error rate. Computer simulations based on the IEEE 802.15.4a channel model also demonstrate the superiority of the proposed algorithm.

• ETRI Journal
• /
• v.45 no.4
• /
• pp.615-626
• /
• 2023

Under limited transmission conditions, many factors affect the efficiency of video transmission. During the flight of an unmanned aerial vehicle (UAV), frequent network switching often occurs, and the channel transmission condition changes rapidly, resulting in low-video transmission efficiency. This paper presents an efficient video coding flow for UAVs working in the 5G nonstandalone network and proposes two bit controllers, including time and spatial bit controllers, in the flow. When the environment fluctuates significantly, the time bit controller adjusts the depth of the recursive codec to reduce the error propagation caused by excessive network inference. The spatial bit controller combines the spatial bit mask with the channel quality multiplier to adjust the bit allocation in space to allocate resources better and improve the efficiency of information carrying. In the spatial bit controller, a flexible mini graph is proposed to compute the channel quality multiplier. In this study, two bit controllers with end-to-end codec were combined, thereby constructing an efficient video coding flow. Many experiments have been performed in various environments. Concerning the multi-scale structural similarity index and peak signal-to-noise ratio, the performance of the coding flow is close to that of H.265 in the low bits per pixel area. With an increase in bits per pixel, the saturation bottleneck of the coding flow is at the same level as that of H.264.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.35 no.2C
• /
• pp.161-171
• /
• 2010

In this paper, we propose an adaptive rate control in Unit-level for real-time H.264/AVC. For given QP, bits according to video characteristics, and current frame is close correlation between the adjacent frames. Using the statistical characteristic, we obtain change of occurrence bit about QP to apply the bit amount by QP from the video characteristic and applied in the estimated bit amount of the each unit of current frame. In addition, we use weight with QP and occurrence bit amount that is statistical information of encoded previous frames. Simulation results show that the proposed rate control scheme achieves time saving of more than 99% over JM 12.1 rate control algorithm. Nevertheless, PSNR and bit rate were almost same as the performances of JM.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.461-462
• /
• 2008

An elaborate Simulink model for a nonredundant 10bit 20MSPS SAR ADC is proposed to verify its algorithm and to consider the real transistor-level issues of analog blocks. Some electrical trade-offs and power issues are considered.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.267-270
• /
• 1999

In this paper, a new method to reduce the size of ROM in the direct digital frequency synthesizer (DDFS) is proposed. In the case that ROM is used for sinusoidal value calculation, reducing the size of ROM is significant. So the power consumption is affected mostly by its bit width. In the proposed method, the ROM bit width is reduced by 1 bit using the phase subtraction and the approximation. The spurious level is better than 80㏈c and the power consumption estimated is 510㎼/MHz.