• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.565-568
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• 1998

The effects of denudation anneals on the properties of 256Mega-bit level devices were investigated. Based on the three-step anneal model, the redistribution of oxygen atom and the defect free zone depth were calculated. A significant outdiffusion of oxygen atoms is occurred during the denudation anneals at high temperature. Junction leakage current of P+/N-Well and N+/P-Well junctions, as a function of denudation anneal temperature, was decreased with increase of anneal temperature and is closely related with the behaviors of oxygen atoms. Also it is found that the denudation anneal at high temperature very effective for the fabrication of reliable 256Mega-bit level devices.

• Proceedings of the Acoustical Society of Korea Conference
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• 1998.06e
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• pp.211-214
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• 1998

TCM(Trellis-Coded Modulation)은 대역폭과 전력이 제한된 채널환경에서 채널부호화 기술과 변조기술을 결합시켜 대역폭의 증가없이 에러정정능력을 개선시키는 통신 기술이다. 본 논문에서는 TCM 신호의 복호시 사용되는 Viterbi decoder에서 traceback depth의 감소에 따른 BER(Bit Error Rate)의 증가를 개선하기 위해 수신부에서 설정하는 traceback depth를 주기로 blocking하여 TCM encoder의 입력시퀀스에 zero padding bits를 추가시키는 새로운 알고리듬을 제안한다. 모의실험결과, traceback depth가 50인 hard decision의 경우 약 2~2.5dB, 4-level soft decision과 8-level soft decision의 경우 약 0.3~2dB의 coding gain을 얻을 수 있었다.

• Journal of IKEEE
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• v.11 no.1 s.20
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• pp.38-45
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• 2007

A new 8-bit single-slope ADC using analog RAMP generator with digitally controllable dynamic range has been proposed and simulated for column level or per-pixel CMOS image sensor application. The conversion gain of ADC can he controlled easily by using frequency divider with digitally controllable diviber ratio, coarse/fine RAMP with class-AB op-amp, resistor strings, decoder, comparator, and etc. The chip area and power consumption can be decreased by simplified analog circuits and passive components. Proposed frequency divider has been implemented and verified with 0.65um, 2-poly, 2-metal standard CMOS process. And the functional verification has been simulated and accomplished in a 0.35$\mu$m standard CMOS process.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.914-917
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• 1999

The paper describes a 17 $\times$ 17-b multiplier using the Radix-4 Booth’s algorithm. which is suitable for 32-bit RISC/DSP microprocessors. To minimize design area and achieve improved speed, a 2-stage pipeline structure is adopted to achieve high clock frequency. Each part of circuit is modeled and optimized at the transistor level, verification of functionality and timing is performed using HSPICE simulations. After modeling and validating the circuit at transistor level, we lay it out in a 0.35 ${\mu}{\textrm}{m}$ 1-poly 4-metal CMOS technology and perform LVS test to compare the layout with the schematic. The simulation results show that maximum frequency is 330MHz under worst operating conditions at 55$^{\circ}C$ , 3V, The post simulation after layout results shows 187MHz under worst case conditions. It contains 9, 115 transistors and the area of layout is 0.72mm by 0.97mm.

• Proceedings of the Korea Inteligent Information System Society Conference
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• 2006.06a
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• pp.311-315
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• 2006

Viterbi decoder는 크게 BM(Branch metric), ACS(Add-Compare-Select), SM(Survivor Memory) block 으로 구성되어 있다. 이중 ACSU 부분은 고속 데이터 처리를 위한 bottleneck이 되어 왔으며, 이의 해결을 위한 많은 연구가 활발히 진행되어 왔다. look ahead technique은 ACSU를 M-step으로 처리하고 CS(Carry save) number를 사용한 새로운 비교 알고리즘을 제안하여 high throughput을 추구했으며, minimized method는 block processing 방식으로 forward, backward 방향으로 decoding을 수행하여 ACSU 부분의 feedback을 완전히 제거하여 exteremely high throughput 을 추구하고 있다. 이에 대해 look ahead technique 의 기본 PE(Processing Element)를 바탕으로 minimized method 알고 리즘의 core block 을 bit-level 로 구현하였으며 : code converter 를 이용하여 CS number 가운데 redundat number(l)를 제거하여 비교기를 더 간단히 하였다. SYNOPSYS의 Design compiler 와 TSMC 0.18 um library 를 이용하여 합성하였다.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.4
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• pp.130-137
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• 1993

In this paper, A progressive coding of mean difference pyramid by Hadamard transform of the difference between two successive pyramid levels has been studied. A block adaptive bit allocation method based on ac energy of each sub-block has been proposed, which efficiently reduces the final distortion in the progressive transmission of image parameters. In our scheme, the dc energy equals the sum of the quantization errors of the Hadamard transform coefficients at previous level. Therefore proposed allocation method includes the estimation of dc energy at each pyramid level. Computer simulation results show some improvements in terms of MSE and picture quality over the conventional fixed allocation scheme.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1995.11a
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• pp.163-172
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• 1995

In this paper, the bit-level 1-dimensionl systolic array for modular multiplication are designed. First of all, the parallel algorithms and data dependence graphs from Walter's Iwamura's methods based on Montgomery Algorithm for modular multiplication are derived and compared. Since Walter's method has the smaller computational index points in data dependence graph than Iwamura's, it is selected as the base algorithm. By the systematic procedure for systolic array design, four 1-dimensional systolic arrays ale obtained and then are evaluated by various criteria. Modifying the array derived from 〔0,1〕 projection direction by adding a control logic and serializing the communication paths of data A, optimal 1-dimensional systolic array is designed. It has constant I/O channels for modular expandable and is good for fault tolerance due to unidirectional paths. And so, it is suitable for RSA Cryptosystem which deals with the large size and many consecutive message blocks.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.51 no.4
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• pp.198-205
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• 2002

In this paper, we proposed a wavelet image coder based on the portable embedded microprocessor. The proposed coder stores the bit level information of the wavelet coefficient in the 2D significance array. Using this information, the coder make the significance check for coefficient and bit level scanning at the same pass. The proposed method has the advantage that we can reduce the scan iteratively and the memory usage for the coding process. Experimental results show that the proposed method outperforms popular image coders such as JPEG, EZW and SPIHT in based on the portable embedded system environment.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.9
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• pp.62-69
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• 1996

In this paper, the bit-level 1-dimensional systolic array for modular multiplication is designed. First of all, the parallel algorithm and data dependence graph from walter's method based on montgomery algorithm suitable for array design for modular multiplication is derived. By the systematic procedure for systolic array design, four 1-dimensional systolic arrays are obtained and then are evaluated by various criteria. As it is modified the array which is derived form [0,1] projection direction by adding a control logic and it is serialized the communication paths of data A, optimal 1-dimensional systolic array is designed. It has constant I/O channels for expansile module and it is easy for fault tolerance due to unidirectional paths. It is suitable for RSA cryptosystem which deals iwth the large size and many consecutive message blocks.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.11
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• pp.111-119
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• 1992

In this paper, we propose an edge detection scheme for noisy images based on the co-occurrence matrix. In the proposed scheme based on the step edge model, the gray level information is simply converted into a bit-map, i.e., the uniform and boundary regions of an image are transformed into a binary pattern by using the local mean. In this binary bit-map pattern, 0 and 1 densely distributed near the boundary region while they are randomly distributed in the uniform region. To detect the boundary region, the co-occurrence matrix on the bit-map is introduced. The effectiveness of the proposed scheme is shown via a quantitative performance comparison to the conventional edge detection methods and the simulation results for noisy images are also presented.