• KSII Transactions on Internet and Information Systems (TIIS)
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• v.6 no.4
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• pp.1128-1139
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• 2012

With the development of three-dimensional display and related technologies, depth video coding becomes a new topic and attracts great attention from industries and research institutes. Because (1) the depth video is not a sequence of images for final viewing by end users but an aid for rendering, and (2) depth video is simpler than the corresponding color video, fast algorithm for depth video is necessary and possible to reduce the computational burden of the encoder. This paper proposes a fast mode decision algorithm for depth video coding based on depth segmentation. Firstly, based on depth perception, the depth video is segmented into three regions: edge, foreground and background. Then, different mode candidates are searched to decide the encoding macroblock mode. Finally, encoding time, bit rate and video quality of virtual view of the proposed algorithm are tested. Experimental results show that the proposed algorithm save encoding time ranging from 82.49% to 93.21% with negligible quality degradation of rendered virtual view image and bit rate increment.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.375-384
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• 2016

In this paper, when stereo image, satellite view and corresponding depth maps were used as the input data, we propose a new method that convert these data to data format suitable for compressing, and then by using these format, intermediate view is synthesized. In the transmitter depth maps are merged to a global depth map and satellite view are converted to residual image corresponding hole region as out of frame area and occlusion region. And these images subsampled to reduce a mount of data and stereo image of main view are encoded by HEVC codec and transmitted. In the receiver intermediate views between stereo image and between stereo image and bit-rate are synthesized using decoded global depth map, residual images and stereo image. Through experiments, we confirm good quality of intermediate views synthesized by proposed format subjectively and objectively in comparison to intermediate views synthesized by MVD format versus total bit-rate.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4C
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• pp.239-246
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• 2005

In this paper. we generate a virtual right image corresponding to the input left image by using given RGB texture data and 8 bit gray scale depth data. We first transform the depth data to disparity data and then produce the virtual right image with this disparity. We also proposed a stereo image synthesis algorithm which is adaptable to a viewer's position and an real-time processing algorithm with a fast LUT(look up table) method. Finally, we could synthesize a total of eleven stereo images with different view points for SD quality of a texture image with 8 bit depth information in a real time.

• Proceedings of the Acoustical Society of Korea Conference
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• 1998.06e
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• pp.211-214
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• 1998

TCM(Trellis-Coded Modulation)은 대역폭과 전력이 제한된 채널환경에서 채널부호화 기술과 변조기술을 결합시켜 대역폭의 증가없이 에러정정능력을 개선시키는 통신 기술이다. 본 논문에서는 TCM 신호의 복호시 사용되는 Viterbi decoder에서 traceback depth의 감소에 따른 BER(Bit Error Rate)의 증가를 개선하기 위해 수신부에서 설정하는 traceback depth를 주기로 blocking하여 TCM encoder의 입력시퀀스에 zero padding bits를 추가시키는 새로운 알고리듬을 제안한다. 모의실험결과, traceback depth가 50인 hard decision의 경우 약 2~2.5dB, 4-level soft decision과 8-level soft decision의 경우 약 0.3~2dB의 coding gain을 얻을 수 있었다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.8
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• pp.33-41
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• 1998

We have designed a high speed and low power 16bit-ELM adder with variable-sized cells uitlizing the fact that the logic depth of lower bit position is less than that of the higher bit position int he conventional ELM architecture. As a result of HSPICE simulation with 0.8.mu.m single-poly double-metal LG CMOS process parameter, out 16bit-ELM adder with variable-sized cells shows the reduction of power-delay-product, which is less than that of the conventional 16bit-ELM adder with reference-sized cells by 19.3%. We optimized the desin with various logic styles including static CMOs, pass-transistor logic and Wang's XOR/XNOR gate. Maximum delay path of an ELM adder depends on the implementation method of S cells and their logic style.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.7
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• pp.2434-2448
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• 2014

This research proposed the domain division depth map quantization for multiview intermediate image generation using Depth Image-Based Rendering (DIBR). This technique used per-pixel depth quantization according to the percentage of depth bits assigned in domains of depth range. A comparative experiment was conducted to investigate the potential benefits of the proposed method against the linear depth quantization on DIBR multiview intermediate image generation. The experiment evaluated three quantization methods with computer-generated 3D scenes, which consisted of various scene complexities and backgrounds, under varying the depth resolution. The results showed that the proposed domain division depth quantization method outperformed the linear method on the 7- bit or lower depth map, especially in the scene with the large object.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.38-47
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• 1999

We have designed a 16bit adder which reduces the power consumption at each level of architecture, logic and transistor. The conventional ELM adder has a major disadvantage which makes glitch in the G cell when the particular input bit patterns are applied, because of the block carry generation signal computed by the input bit pattern. Thus, we propose a low power adder architecture which can automatically transfer each block carry generation signal to the G cell of the last level to avoid glitches for particular input bit patterns at the architecture level. We also use a combination of logic styles which is suitable for low power consumption with static CMOS and low power XOR gate at the logic level. Futhermore, The variable-sized cells are used for reduction of power consumption according to the logic depth of the bit propagation at the transistor level. As a result of HSPICE simulation with $0.6\mu\textrm{m}$ single-poly triple-metal LG CMOS standard process parameter, the proposed adder is superior to the conventional ELM architecture with fixed-sized cell and fully static CMOS by 23.6% in power consumption, 22.6% in power-delay-product, respectively.

• Journal of the Korean Society for Precision Engineering
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• v.12 no.9
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• pp.74-85
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• 1995

The purpose of this paper is to evaluate the grade of WA vitrified and resinoid bond grinding wheels by the sue of AE measuring system. When the manufactured 48 kinds of specimens were scratched by the method of OKOSHI'S grade test, the relationship between the amount of bit scratch depth of grinding wheel specimens and the character- istics of AE signals, and the relationship of AE counts and grade were considered as fololws; (1) The higher the grades are AE cumlulative event counts N and AE event count rate n, the smaller the values tend to be. But A $E_{rms}$is in reverse. (2) In the case of same grade, the smaller the grain size is, the higher the value of AE cumulative event counts N and A $E_{rms}$is results of comparison and observation. The grinding wheel with lower elasticity and with higher percentage of pore detected higher value of AE cumula- tive event counts N than with higher elasticity and lower percentage of pore. But A $E_{rms}$ is in reverse. (3) AE cumulative event counts N and bit scratch depth h have normally one to one correspondence. (4) It can be expected that quantitative evaluations of grade by using AE have been carried out by the wave observation of AE signal in line with the relationship between load speed of bit and AE cumulative event counts N & AE event count rate n.' AE event count rate n.ate n.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.11-20
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• 2008

The structure of 2-bit/cell flash memory device was characterized for sub-50 nm non-volatile memory (NVM) technology. The memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region, and is erased (or programmed) by using band-to-band tunneling hot-hole injection (or channel hot-electron injection). It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the $V_{th}$ margin for 2-bit/cell operation by ${\sim}2.5$ times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the $V_{th}$ margin more than ${\sim}1.5V$. For a bit-programmed cell, reasonable bit-erasing characteristics were shown with the bias and stress pulse time condition for 2-bit/cell operation. The length effect of the spacer-type storage node is also characterized. Device which has the charge storage length of 40 nm shown better ${\Delta}V_{th}$ and $V_{th}$ margin for 2-bit/cell than those of the device with the length of 84 nm at a fixed recess depth of 100 nm. It was shown that peak of trapped charge density was observed near ${\sim}10nm$ below the source/drain junction.

• ETRI Journal
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• v.45 no.4
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• pp.615-626
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• 2023

Under limited transmission conditions, many factors affect the efficiency of video transmission. During the flight of an unmanned aerial vehicle (UAV), frequent network switching often occurs, and the channel transmission condition changes rapidly, resulting in low-video transmission efficiency. This paper presents an efficient video coding flow for UAVs working in the 5G nonstandalone network and proposes two bit controllers, including time and spatial bit controllers, in the flow. When the environment fluctuates significantly, the time bit controller adjusts the depth of the recursive codec to reduce the error propagation caused by excessive network inference. The spatial bit controller combines the spatial bit mask with the channel quality multiplier to adjust the bit allocation in space to allocate resources better and improve the efficiency of information carrying. In the spatial bit controller, a flexible mini graph is proposed to compute the channel quality multiplier. In this study, two bit controllers with end-to-end codec were combined, thereby constructing an efficient video coding flow. Many experiments have been performed in various environments. Concerning the multi-scale structural similarity index and peak signal-to-noise ratio, the performance of the coding flow is close to that of H.265 in the low bits per pixel area. With an increase in bits per pixel, the saturation bottleneck of the coding flow is at the same level as that of H.264.