• ETRI Journal
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• v.31 no.5
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• pp.613-615
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• 2009

We propose a pilot-based coding (PBC) scheme for lossless bit rate reduction of parametric stereo (PS) in enhanced aacPlus. It uses PBC in addition to the existing frequency and time differential coding to encode and decode PS parameter indexes. We also design optimal Huffman codebooks (HCBs) for PBC in the proposed scheme. Experiments show that the proposed scheme is superior to the original coding scheme, where both the new coding structure and the optimal HCBs contribute to the bit rate reduction.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.165-168
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• 2000

A hardware architecture to implement the SEED block cipher algorithm into one chip is described. Each functional unit is designed with VHDL hardware description language and synthesis tools. The designed hardware receives a 128-bit block of plain text input and a 128-bit key, and generates a 128-bit cipher block after 16-round operations after 8 clocks. The encryption time is within 20 nsec.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.2
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• pp.1-8
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• 1992

This paper is proposed a Modified WLD (Weighted Levenshtein Distance) algorithm for processor desihn of code-string matching. A proposed MWLD (Modified Weighted Levenshtein Distance) algorithm is consist of 1-dimension bit-serial array processor to pattern matching using a Hamming Distance. The proposed processor is applied to recognition of character with real time input. The recognition rate of Hangul strokes is resulted to 98.65$\%$

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.801-804
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• 2005

In this paper, we designed an 8-bit color adjustor for SDTV using Verilog HDL. The conversion block requires a lot of multiplication. So we adopted Booth algorithm to reduce amount of operation and processing time. To improve speed, we designed the system output as parallel structure. We synthesized the designed system using Xilinx ISE and verified the operation through simulation using Modelsim.

• 제어로봇시스템학회:학술대회논문집
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• 1988.10a
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• pp.82-85
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• 1988

This paper are the manufacture of controller of direct drive arm robot using 32 bit CPU(MC 69020). The work would draw on KIT of Robotics Laboratory whose extensive experience in 16 bit CPU Controller(MC 68008) in addition to the WHILE languages. We found that this controller is good for the direct drive arm robot controller for the use of self-tuning algorithms and real time control.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.371-374
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• 2000

This paper proposes a 16-bit ${\times}$ 16-bit multiplier for 2 twos-complement binary numbers with tree-like structure and implements it on a FPGA. The space and time complexity analysis shows that the 16-bit Tree-like multiplier represents lower circuit complexity and computes more quickly than both Booth array multiplier md Modified array multiplier.

• The Journal of Internal Korean Medicine
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• v.25 no.4
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• pp.274-288
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• 2004

Objectives : This study was designed to evaluate the effect on cytotoxicity of Bojungikki-tang(BIT) in human lung cancer H460 cells. Methods : BIT-induced cell death was confirmed as apoptosis characterized by chromatin condensation and increase of the $sub-G_1$, DNA content. It was tested whether the water extract of BIT affects the cell cycle regulators such as, p2l/Cipl, p27/Kipl, cyclin $B_1$. Results : The data showed that treatment of BIT decreased the viability of H460 cells in a dose-dependent manner. p2l/Cip1 is gradually decreased by the addition of the cells with BIT extract. Interestingly, p27/Kip1 is not detected for 24 hr after the addition of BIT extract, however, after 24 hr, p27/Kipl markedly increased. In addition, cyclin $B_1$, decreased in a time dependent manner after the addition of the water extract. The activation of caspase -3 protease was further confirmed by degradation of procaspase-8 protease andpoly(ADP-ribose) polymerase(P ARP) by BIT in H460 cells. Moreover, BIT induced the increase of Bak expression. Conclusion : These results suggest that the extract of BIT exerts anticancer effects to induce the death of human lung cancer H460 cells via down regulation of cell cycle regulators such as p2l/Cip1, and cyclin B1 or up regulation of cell cycle regulators such as p27/Kip1. Moerover results suggest that BIT induces an apoptosis in H460 cells via activation of intrinsic caspase cascades.

• Progress in Superconductivity
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• v.7 no.2
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• pp.109-113
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• 2006

The Arithmetic Logic Unit (ALU) is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We have developed and tested an RSFQ multi-bit ALU constructed with half adder unit cells. To reduce the complexity of the ALU, We used half adder unit cells. The unit cells were constructed of one half adder and three de switches. The timing problem in the complex circuits has been a very important issue. We have calculated the delay time of all components in the circuit by using Josephson circuit simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. For high-speed tests, we used an eye-diagram technique. Our 4-bit ALU operated correctly at up to 5 GHz clock frequency.

• Journal of Institute of Control, Robotics and Systems
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• v.22 no.8
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• pp.671-677
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• 2016

A Controller Area Network (CAN) is a serial communication protocol that is highly reliable and efficient in many aspects, such as wiring cost and space, system flexibility, and network maintenance. Therefore, it is chosen for the communication protocol between a single chip controller based on Field Programmable Gate Array (FPGA) and peripheral devices. In this paper, the design and implementation of CAN IP, which is written in VHSIC Hardware Description Language (VHDL), is presented. The implemented CAN IP is based on the CAN 2.0A specification. The CAN IP consists of three processes: clock generator, bit timing, and bit streaming. The clock generator process generates a time quantum clock. The bit timing process does synchronization, receives bits from the Rx port, and transmits bits to the Tx port. The bit streaming process generates a bit stream, which is made from a message received from a micro controller subsystem, receives a bit stream from the bit timing process, and handles errors depending on the state of the CAN node and CAN message fields. The implemented CAN IP is synthesized and downloaded into SmartFusion FPGA. Simulations using ModelSim and chip test results show that the implemented CAN IP conforms to the CAN 2.0A specification.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.55-58
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• 2008

RFID(Radio frequency IDentification) leader is collision of data, when recognizing the multiple tag the inside area. This collision became the cause which delays the tag recognition time of the leader. The protocol which prevents the delay of tag recognition time of the leader the place where representative it uses QT(Query Tree) algorithms, it uses a collision bit position from this paper and are improved QT-MTC(Query Tree with Multi-Tag Cognition) algorithms which it proposes. This algorithm stored the bit position which bit possibility and the collision where the collision happens occurs in the stack and goes round a tree the number of time which, it reduced could be identified two tags simultaneously in order, it was planned. A result of performance analysis, It compared in QT protocols and the this algorithm against the tag bit which is continued a tush efficiency improvement effect was visible.