• The Journal of the Acoustical Society of Korea
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• v.20 no.3
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• pp.42-47
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• 2001

This paper improves the performance of VAD (Voice Activity Detector) in G.723.1 Annex A 6.3kbps/5.3kbps dual rate speech coder, which is developed for Internet Phone and videoconferencing. The VAD decision is based on a three-level energy threshold. We evaluates for processing time, speech quality, and bit rate. The processing time is reduced due to the accuracy of VAD decision on the silence period. On subjective quality test there is almost no difference compared with the G.723.1. In order to measure the bit rate we count the active speech frame (VAD=1) and we can reduce more bit rate as silence periods are shown.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.11
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• pp.643-649
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• 2005

A heart diagnosis system adopts Superconducting Quantum Interface Device(SQUD) sensors for precise MCG(MagnetoCardioGram) signal acquisitions. Such system needs to deal with hundreds of sensors, requiring fast signal sampling md precise analog-to-digital conversions(ADC). Our development of hardware board, processing 64-channel 12-bit in 1 ks/s speed, is built by using 8-channel ADC chips, 8-bit microprocessors, SPI interfaces, and specially designed parallel data transfers between microprocessors to meet the 1ks/s, i.e. 1 mili-second sampling interval. We extend the design into 256-channel hardware and analyze the speed .using the measured data from the 64-channel hardware. Since our design exploits full parallel processing, Assembly level coding, and NOP(No Operation) instruction for timing control, the design provides expandability and lowest system timing margin. Our result concludes that the data collection with 256-channel analog input signals can be done in 201.5us time-interval which is much shorter than the required 1 mili-second period.

• Journal of the Korea Society of Computer and Information
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• v.22 no.5
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• pp.1-9
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• 2017

Recently, flash memory has been in a great demand from embedded system sectors for storage devices. However, program/erase (P/E) cycles per block are limited on flash memory. For the limited number of P/E cycles, many wear leveling techniques are studied. They prolonged the life time of flash memory using information tables. As one of the techniques, block erase table (BET) method using a bit array table was studied for embedded devices. However, it has a disadvantage in that performance of wear leveling is sharply low, when the consumption of memory is reduced. To solve this problem, we propose a novel wear leveling technique using Sampling-based Block Erase Table (SBET). SBET relates one bit of the bit array table to each block by using exclusive OR operation with round robin function. Accordingly, SBET enhances accuracy of cold block information and can prevent to decrease the performance of wear leveling. In our experiment, SBET prolongs life time of flash memory by up to 88%, compared with previous techniques which use a bit array table.

• IEMEK Journal of Embedded Systems and Applications
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• v.8 no.5
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• pp.285-293
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• 2013

The procedure of the arbitration which is the tag collision is essential because the multiple tags response simultaneously in the same frequency to the request of the Reader. This procedure is known as Anti-collision and it is a key technology in the RFID system. In this paper, we propose the Bit Pattern Prediction Algorithm(BPPA) for the efficient identification of the multiple tags. The BPPA is based on the tree algorithm using the time slot and identify the tag quickly and efficiently using accurate bit pattern prediction method. Through mathematical performance analysis, We proved that the BPPA is an O(n) algorithm by analyzing the worst-case time complexity and the BPPA's performance is improved compared to existing algorithms. Through MATLAB simulation experiments, we verified that the BPPA require the average 1.2 times query per one tag identification and the BPPA ensure stable performance regardless of the number of the tags.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.161-162
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• 2011

Recently, many research works are focusing on DVC (Distributed Video Coding) system for low complexity encoder. However the feedback channel-based parity bit control is a major cause of the high decoding time latency. Spatial and temporal correlation is high in video and, therefore, the statistical property can be applied for the parity bit request of LDPCA frame. By introducing frame adaptive parity bit request estimation method, this paper proposes a new method for reducing the decoding time latency. Through computer simulations, it is shown that the proposed method achieves about 80% of complexity reduction, compared to the conventional no-estimation method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.5A
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• pp.317-324
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• 2012

Physical layer network coding (PNC) was first introduce by Zhang et al. for two-way relay channels (TWRCs). By utilizing the PNC, we can complete two-way communications within two time slots, instead of three time slots required in non-PNC systems. Recently, the upper and lower bounds for a bit error rate (BER) of PNC have been analyzed for fading channels. In this paper, we derive an exact BER of the PNC for the TWRC over fading channels. We determine decision regions based on the nearest neighbor rule and partition them into several wedge areas to apply the Craig's polar coordinate form for computing the BER. We confirm that our derived analysis accurately matches with the simulation results.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.886-889
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• 2014

In this paper, we evaluate a physical layer security performance of orthogonal space-time block code(OSTBC) using one-bit feedback in the presence of an eavesdropper in wiretap channels, where we assume spatially correlated MIMO(multiple-input multiple-output) channels. In this paper, we present the one-bit feedback based OSTBC(F-OSTBC) scheme and compare security outage performances of F-OSTBC, conventional OSTBC, and transmission antenna selection schemes for various spatial correlation conditions at each node.

• Journal of KIISE:Software and Applications
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• v.27 no.5
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• pp.543-550
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• 2000

An adaptive bit-reduced mean absolute difference (ABRMAD) is presented as a criterion for the block-matching algorithm (BMA) to reduce the complexity of the VLSI Implementation and to improve the processing time. The ABRMAD uses the lower pixel resolution of the significant bits instead of full resolution pixel values to estimate the motion vector (MV) by examining the pixels Ina block. Simulation results show that the 4-bit ABRMAD has competitive mean square error (MSE)results and a half less hardware complexity than the MAD criterion, It has also better characteristics in terms of both MSE performance and hardware complexity than the Minimax criterion and has better MSE performance than the difference pixel counting(DPC), binary block-matching with edge-map(BBME), and bit-plane matching(BPM) with the same number of bits.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.66.1-66.1
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• 2012

Although all printed cost-less radio frequency identification (RFID) tags have been considered as a core tool for bringing up a ubiquitous society, the difficulties in integrating thin film transistors (TFTs), diodes and capacitors on plastic foils using a single in-line printing method nullify their roles for the realization of the ubiquitous society1,2. To prove the concept of all printed cost-less RFID tag, the practical degree of the integration of those devices on the plastic foils should be successfully printed to demonstrate multi bit RFID tag. The tag contains key device units such as 13.56 MHz modulating TFT, digital logic gates and 13.56 MHz rectifier to generate and transfer multi bit digital codes via a wireless communication (13.56 MHz). However, those key devices have never been integrated on the plastic foils using printing method yet because the electrical fluctuation of fully printed TFTs and diodes on plastic foils could not be controlled to show the function of desired devices. In this work, fully gravure printing process in printing 13.56 MHz operated 32 bit RFID tags on plastic foils has been demonstrated for the first time to prove all printed RFID tags on plastic foils can wirelessly generate and transfer 32 bit digital codes using the radio frequency of 13.56 MHz. This result proved that the electrical fluctuations of printed TFTs and diodes on plastic foils should be controlled in the range of maximum 20% to properly operate 32 bit RFID tags.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.1
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• pp.146-150
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• 2009

Nowdays needs the new still image compression standard. JPEG2000 has been developed. JPEG2000 divide DWT and EBCOT. EBCOT is consisted of Bit Plane Coding and ARithmetic Coding algorithm. In this paper, we proposed BPC algorithm that is efficient context-based generation. Proposed BPC Algorithm forecasted coding pass using SigStage, column, mpass value. BPC designed using Verilog HDL. H/W implemenates using Xillinx FPGA technology.