• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.393-394
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• 2006

This paper lists various error resilience tools and analyzes performance in IP Datacast over DVB-H systems and schemes are proposed. Experiments shows that, in DVB-H environment, encoding with macroblock line intra update can achieve the best error correction ability, because this tool can make full use of spatial correlation for intra prediction and reduce the requirement of bit rate.

• ETRI Journal
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• v.26 no.6
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• pp.635-640
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• 2004

A new low-complexity differential detection technique, fractional multi-bit differential detection (FMDD), is proposed in order to improve the performance of continuous phase modulation (CPM) signals such as Gaussian minimum shift keying (GMSK) and Gaussian frequency shift keying (GFSK). In comparison to conventional one-bit differential detected (1DD) GFSK, the FMDD-employed GFSK provides a signal-to-noise ratio advantage of up to 1.8 dB in an AWGN channel. Thus, the bit-error rate performance of the proposed FMDD is brought close to that of an ideal coherent detection while avoiding the implementation complexity associated with the carrier recovery. In the adjacent channel interference environment, FMDD achieves an even larger SNR advantage compared to 1DD.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.201-204
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• 2000

In this paper, an A/D converter is implemented to obtain 8bit resolution at a conversion rate of 10Msample/s. This architecture is proposed using the 2-step architecture for high speed conversion rate. It is consisted of sample/hold circuit, low power comparator, voltage reference circuit and DAC of binary weighted capacitor array. Proposed A/D converter is designed using 0.2$\mu\textrm{m}$ CMOS technology. The SNR is 45.3dB at a sampling rate of 10MHz with 1.95MHz sine input signal. When an 8bit 10Msample/s A/D converter is simulated, the Differential Nonlinearity / Integral Nonlinearity (DNL/ INL) error are ${\pm}$1 / ${\pm}$2 LSB, respectively. The power consumption is 13㎽ at single +2.5V supply voltage.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1215-1218
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• 1998

본 논문은 Digital Audio Compression(AC-3) Standard 인 A-52를 기반으로 하였으며 Borland C++3.1 Compiler를 사용하여 AC-3 Decoding Algorithm 구현하였다. Input Stream은 DVD VOB File에서 AC-3 Stream만을 분리하여 사용하며 최종 출력은 16 Bit PCM File이다. AC-3의 Frame구조는 Synchronization Information, Bit Stream Information, Audio Block, Auxiliary Data, Error Check로 구성된다. Aduio Block 은 모두 6개의 Block으로 나뉘어져 있다. BSI와 Side Information을 참조하여 Exponent를 추출하여 Exponent Strategy에 따라 Exponent를 복원한다. 복원된 Exponent 정보를 이용하여 Bit Allocation을 수행하여 각각의 Mantissa에 할당된 Bit수를 계산하고 Stream으로부터 Mantissa를 추출한다. Coupling Parameter를 참조하ㅕ Coupling Channel을 Original Channel로 복원시킨다. Stereo Mode에 대해서는 Rematrixing을 수행한다. Dynamic Range는 Mantissa와 Exponent의 Magnitude를 바꾸는 것으로 선택적으로 사용할 수 있다. Mantissa와 Exponent를 결합하여 Floating Point coefficient로 만든 후 Inverse Transform을 수행하면 PCM Data를 얻을 수 있다. PC에서 듣기 위해서는 Multi Channel을 Stereo나 Mono로 Downmix를 수행한다. 이렇게 만들어진 PCM data는 PCM Data를 재생하는 프로그램으로 재생할 수 있다.

• Journal of Korea Society of Digital Industry and Information Management
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• v.4 no.4
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• pp.9-19
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• 2008

In this paper, it is studied anti-collision algorithm based on the transmission protocol for RFID baseband system of the lSO/IEC 18000-6 Type-C regulation and designed the baseband part of RFID reader system using FPGA. To compensate this weak point of the slot random aloha algorithm which must have a long time to be dumped before deciding an appropriate slot size according to the number of surrounding tag, we suggested how to apply Bit By Bit algorithm to be able to recognize the tag when the tag is clashing. The design of the baseband part in the RFID reader system is accomplish by use of the ISE9.1i and I made an experiment on it targeting Spartan2. Construction verification is measured each block through Logic Analyzer and I can verify it has no error. I also compared and analyzed the performance between proposed algorithm and past algorithm and verified the improvement of performance.

• 한국정보통신설비학회:학술대회논문집
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• 2002.08a
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• pp.27-30
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• 2002

10-bit 해상도, 10MS/s의 ADC를 Stage 당 1.5-Bit의 Resolution을 가지는 Redundant signed digit(RSD) 방식의 파이프라인 구조를 이용하여 설계하였다. Error Correction Logic을 사용함으로써 비교기를 Coarse하게 설계하였고 잔류 전압 증폭기의 최적 Scaling을 통하여 일반적인 ADC에 비해 성능 저하 없이 효율적으로 소비 전력을 감소시켰다. 또한, Charge Pump의 선택적 사용을 통해 기생 커패시턴스의 영향을 최소화함으로써 잔류전압 증폭기의 출력 전압 특성을 향상 시켰다. 삼성 0.35u CMOS 공정 파라미터를 이용하여 입력 전압 $-1{\sim}1V$, 공급 전압 $-1.5{\sim}1.5V$에서 18.73mW로 설계하였으며 HSPICE로 시뮬레이션 하였다.

• Journal of Communications and Networks
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• v.7 no.4
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• pp.462-470
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• 2005

We propose a multi-rate and multi-BEP transmission scheme using adaptive overlapping pulse-position modulator (OPPM) and optical power controller in optical code division multiple access (CDMA) networks. The proposed system achieves the multi-rate and multi-BEP transmission by accommodating users with different values of OPPM parameter and transmitted power in the same network. The proposed scheme has advantages that the system is not required to change the code length and number of weight depending on the required bit rate of a user and the difference of bit rates does not have so much effect on the bit error probabilities (BEPs). Moreover, the difference of transmitted powers does not cause the change of bit rate. We analyze the BEPs of the four multimedia service classes corresponding to the com­binations of high/low-rates and low/high-BEPs and show that the proposed scheme can easily achieve distinct differentiation of the service classes with the simple system configuration.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.21-24
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• 2000

This paper introduces the design and implementation of a Ku-band 5-bit monolithic phase shifter with a ceramic package. The 5-bit phase shifter MMIC was designed and fabricated by using GaAs MESFET switches. The packaged phase shifter demonstrates a phase error less than 11.3 $^{\circ}$ RMS and an insertion loss variation less than 1.0㏈ RMS for 13∼15㎓. For all 32 states, an insertion loss is measured to be 12.2${\pm}$2.2㏈, an input return loss more than 5.0㏈, and an output return loss more than 6.2㏈ from 13㎓ to 15㎓. The chip size of the 5-bit phase shifter MMIC is 2.35${\times}$1.65mm$\^$2/ including digital control circuits. The size of the ceramic packaged phase shifter is 7.2${\times}$6.2mm$\^$2/.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.263-266
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• 1999

In this work, a A/D converter is implemented to obtain 8bit resolution at a conversion rate of 10MS/s for video applications. This architecture is proposed using the Pipelined architecture for high speed conversion rate and the Successive - Approximation architecture for low power consumption, and consists of two identical stages that consist of sample/hold circuit, low power comparator, voltage reference circuit and MDAC of binary weighted capacitor array. Proposed A/D converter is designed using 0.25${\mu}{\textrm}{m}$ CMOS technology The SNR is 80㏈ at a sampling rate of 10MHz with 1.95MHz sine input signal. When an 8bit 10MS/s A/D converter is simulated, the Differential Nonlinearity / Integral Nonlinearity (DNL/ INL) error are $\pm$0.5 / $\pm$2 LSB, respectively. The power consumption is 13㎽ at 10MS/s.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2056-2059
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• 2003

The rate control is very important to solve the difficulties arising from bit-rate on transmission through channel and to improve video quality. It is very important to point out that the amount of output bit obtained the encoding process using rate controller brings many problems on the transmission of channels and furthermore output bitstream decoded affects directly on the visual quality of displayed subject. In this paper, the effective rate control algorithm by rate-distortion modeling using MPEG-4 encoder is proposed. The proposed rate control has applied different weighting by VOP prediction type and even in the same VOP prediction type, the predicted reference allocates more bit. Through these bit allocation the minimization of distortion can be achieved preventing propagation of quantization error The amount of saved bitstream obtained by the proposed algorithm in this thesis is allocated to I-VOP using region of interest(ROI) selective enhancement on the next GOV encoding process and this process brought the improvement of visual quality.