• Korean Journal of Optics and Photonics
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• v.14 no.2
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• pp.150-154
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• 2003

In this paper, we introduce modified parity coding methods to reduce the errors caused by spatial beam intensity variations in a holographic data storage system. We explained the encoding and decoding process of the conventional parity coding and the modified parity coding techniques. We compared the bit-error-rate (BER) performances of the conventional parity coding and the modified parity coding techniques from experimental evaluation.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.315-319
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• 2011

A switched-capacitor cyclic DAC scheme with mismatch compensation of capacitors is designed. In cyclic DAC, a little error between two capacitors is accumulated every cycle. As a result, the accumulated error influences the final analog output which is wrong data. Therefore, a mismatch compensation technique was proposed and the error can be effectively reduced, which alleviates the matching requirement. In order to verify the operation of the proposed DAC, an 8-bit switched-capacitor cyclic DAC is designed through HSPICE simulation and implemented through magna 0.18um standard CMOS process.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3239-3241
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• 1999

Two-dimensional optical code-division multiple access is a system to transmit a two- dimensional data via parallel transmission line. The probability density function (pdf) of interference noise from other users is calculated and the pdf of asynchronous interference noise is newly calculated to present lower bounds of probability of error. The corresponding bit error rate is evaluated from this results.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.4 no.2
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• pp.369-378
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• 2014

The Reed-Muller code is one of the efficient algorithms for multiple bit error correction, however, its high-computation requirement inherent in the decoding process prohibits its use in practical applications. To solve this problem, this paper proposes a graphics processing unit (GPU)-based parallel error control approach using Reed-Muller R(r, m) coding for real-time wireless communication systems. GPU offers a high-throughput parallel computing platform that can achieve the desired high-performance decoding by exploiting massive parallelism inherent in the algorithm. In addition, we compare the performance of the GPU-based approach with the equivalent sequential approach that runs on the traditional CPU. The experimental results indicate that the proposed GPU-based approach exceedingly outperforms the sequential approach in terms of execution time, yielding over 70× speedup.

• Journal of KIISE:Information Networking
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• v.30 no.6
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• pp.695-704
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• 2003

A wavelet-based video stream is more susceptible to the network transmission errors than DCT-based video. This is because bit-errors in a subband of a video frame affect not only the other subbands within the current frame but also the subsequent frames. In this paper, we propose a video source coding scheme called IPC(Intra Prediction Coding) scheme in order to reduce the error propagation to the subsequent frames. In the proposed scheme, a subband except LL subband in the current frame refers to the lower-level subband within the same frame. This reduces the error propagation to subsequent frames. We evaluated the performance of our proposed scheme in the simulated wireless network environment. As a result of tests, it was shown that the proposed algorithm shows better performance than MRME in a heavy motion image sequence while IPC outperforms MRME at a high bit-rate in small motion image sequence.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.6B
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• pp.948-953
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• 2010

In this paper, we propose multi-bit soft error detection method which can use an instruction cache of superscalar CPU architecture. Proposed method is applied to high-speed static RAM for instruction cache. Using 1D parity and interleaving, it has less memory overhead and detects more multi-bit errors comparing with other methods. It only detects occurrence of soft errors in static RAM. Error correction is treated like a cache miss situation. When soft errors are occurred, it is detected by 1D parity. Instruction cache just fetch the words from lower-level memory to correct errors. This method can detect multi-bit errors in maximum 4$\times$4 window.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.4
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• pp.712-720
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• 1994

In digital mobile communication systems, the convolutional coding is considered as the optimum error correcting scheme. Recently, the Viterbi algorithm is widely used for the decoding of convolutional code. Most Viterbi decoder has been proposed in conde rate R=1/2 or 2/3 with memory components (m) less than 3. which degrades the error correcting capability because of small code constraints (K). We consider the design method for typical code rate R=1/2, K=7(171,133) convolutional code with memory components, m=6. In this paper, a novel construction method is presented which combines maximum likelihood decoding with a state transition double detection and comparison method. And the designed circuit has the error-correcting capability of random 2 bit error. As the results of logic simulation, it is shown that the proposed Viterbi decoder exactly corrects 1 bit and 2 bit error signal.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2005.11a
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• pp.353-356
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• 2005

In this paper, the proposed $gamma({\gamma})$ line system is developed for reducing the error between non-linear gamma curve produced by a formula and result produced by hardware implementation. The proposed algorithm and system is based on the specific gamma value 2.2, namely the formula is represented by {0,1}$^{2.2}$ and the bit width of input and out data is 10bit. In order to reduce the error, the system is using least squares polynomial of the numerical method which is calculating the best fitting polynomial through a set of points. The proposed gamma line is consisting of nine kinds of quadratic equations, each with their own overlap sections to get more precise. Based on the algorithm verified by $MATLAB^{TM}$ 7.0, the proposed system is implemented by using Verilog-HDL. The proposed system has 2 clock latency; 1 result per clock. The error range (LSB) is -4 and +3. Its standard deviation is 1.287956238. The total gate count of system is 2,083 gates and the maximum timing is 15.56[ns].

• The KIPS Transactions:PartC
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• v.15C no.5
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• pp.399-408
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• 2008

Mobile WiMAX provides wireless broadband services for data communication based on IP protocol. The limitation of physical bandwidth in the radio links may cause performance degradation in providing wireless broadband services in WIMAX. To enhance the efficiency of the radio link utilization, Payload Header Suppression (PHS) is defined as an optional header compression mechanism for mobile WiMAX. It has, however, a very limited compression capability since it has very restrictive compression fields. In this paper, hence, we assumed the application of Robust Header Compression (ROHC), a header compression scheme proposed for links characterized by high bit error ratios, long round-trip times (RTT), and scarce resource, to Mobile WiMAX, and studied its performance. Previous studies on ROHC performance merely focused on the impact of high bit error rate. However, bit error is virtually transparent to ROHC in the wireless systems like WiMAX, since the MAC provides the bit error checking function. In order to evaluate the performance of ROHC in the Mobile WiMAX environments, therefore, we evaluated the performance of ROHC with respect to the packet losses instead of bit error. We investigated the impact of the ROHC parameters that are recommended for the implementation in the ROHC and compared the performance of ROHC with PHS.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.8C
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• pp.832-837
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• 2005

This paper presents a design method for fixed-width squarer that receives a W-bit input and produces a W-bit squared product. To efficiently compensate for the quantization error, modified Booth encoder signals (not multiplier coefficients) are used for the generation of error compensation bias. The truncated bits are divided into two groups (major/minor group) depending upon their effects on the quantization error. Then, different error compensation methods are applied to each group. By simulations, it is shown that the performance of the proposed method is close to that of the rounding method and much better than that of the truncation method and conventional method. It is also shown that the proposed method leads to up to $28\%\;and\;27\%$ reduction in area and power consumption compared with the ideal squarers, respectively.