• ETRI Journal
• /
• v.45 no.4
• /
• pp.615-626
• /
• 2023

Under limited transmission conditions, many factors affect the efficiency of video transmission. During the flight of an unmanned aerial vehicle (UAV), frequent network switching often occurs, and the channel transmission condition changes rapidly, resulting in low-video transmission efficiency. This paper presents an efficient video coding flow for UAVs working in the 5G nonstandalone network and proposes two bit controllers, including time and spatial bit controllers, in the flow. When the environment fluctuates significantly, the time bit controller adjusts the depth of the recursive codec to reduce the error propagation caused by excessive network inference. The spatial bit controller combines the spatial bit mask with the channel quality multiplier to adjust the bit allocation in space to allocate resources better and improve the efficiency of information carrying. In the spatial bit controller, a flexible mini graph is proposed to compute the channel quality multiplier. In this study, two bit controllers with end-to-end codec were combined, thereby constructing an efficient video coding flow. Many experiments have been performed in various environments. Concerning the multi-scale structural similarity index and peak signal-to-noise ratio, the performance of the coding flow is close to that of H.265 in the low bits per pixel area. With an increase in bits per pixel, the saturation bottleneck of the coding flow is at the same level as that of H.264.

• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.403-406
• /
• 1999

Among the compression methods of moving picture information, a motion estimation method is used to remove time-repeating. The Block Matching Algorithm in motion estimation methods is the commonest one. In recent days, it is required the more advanced high quality in many image processing fields, for example HDTV, etc. Therefore, we have to accomplish not by means of Partial Search Algorithm, but by means of Full Search Algorithm in Block Matching Algorithm. In this paper, it is suggested a structure that reduce total calculation quantity and size, because the structure using Bit Plane select and use only 3bit of 8bit luminance signal.

• Proceedings of the IEEK Conference
• /
• 2001.06a
• /
• pp.309-312
• /
• 2001

In this paper, we proposed a system for bit stream wireless communication using audio/video infrared transceiver and implemented a circuit. The proposed transmitter system converted bit stream into analog signal format that is similar to NTSC. Then the analog signal can be transmitted by infrared spatial coupler for A/V signals. And the receiver system recover the bit stream by inverse process of transmitter.

• Proceedings of the IEEK Conference
• /
• 2002.07a
• /
• pp.349-352
• /
• 2002

This paper describes a design of a 1bit Carry Propagate Free Adder/Subtracter (CPFA/S) VLSI using the Adiabatic Dynamic CMOS Logic (ADCL) circuit technology. Using a PSPICE simulator, energy dissipation of the ADCL 1bit CPFA/S is compared with that of the CMOS 1bit CPFA/S. As a result, energy dissipation of the proposed ADCL circuits is about 1/23 as low as that of the CMOS circuits. The transistors count, propagation-delay tittle and energy dissipation of the ADCL 4bit CPFA/S are compared with those of the ADCL 4bit Carry Propagate Adder/Subtracter (CPA/S). The transistors count and propagation-delay tittle are found to be reduced by 7.02% and 57.1%, respectively. Also, energy dissipation is found to be reduced by 78.4%. Circuit operation and performance are evaluated using a chain of the ADCL 1bit CPFA/S fabricated in a $1.21mutextrm{m}$ CMOS process. The experimental results show that addition and subtraction are operated with clock frequencies up to about 1㎒.

• Proceedings of the KIEE Conference
• /
• 2003.11b
• /
• pp.75-78
• /
• 2003

In this paper, a second-order 3-bit DSM using DWA(Data Weighted Averaging) algorithm is designed for bluetooth Zero-IF Receiver. The designed circuit has two integrators using a designed OTA, nonoverlapping two-phase clerk generator, 3-bit A/D converter, DWA algorithm and 3-bit D/A converter An ideal model of second-order lowpass DSM with a 3-bit quantizer was configured by using MATLAB, and each coefficients and design specification of each blocks were determined to have 10-bit resolution in 1MHz channel bandwidth. The designed second-order 3-blt lowpass DSM has maximum SNR of 74dB and power consumption is 50mW at 3.3V.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.6
• /
• pp.821-828
• /
• 1990

A forward error correction (FEC) technique is presented for speech data in 16 Kbps digital mobile communications. 14Kbps SBC-APCM(AQB) and QPSK are used as speech coding and modulation techniques, respectively. Because each bit in a speech data block had different importance, applying FEC to speech data bit-selectively in more effective than applying FEC to all speech data equally. To select bits in a speech data block to be protected by FEC the bit error sensitivity of each bit is computed. For a few BCH and Reed-Solomon codes used as bit-selective FEC the performance of the coding technique is computed.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.8
• /
• pp.33-41
• /
• 1998

We have designed a high speed and low power 16bit-ELM adder with variable-sized cells uitlizing the fact that the logic depth of lower bit position is less than that of the higher bit position int he conventional ELM architecture. As a result of HSPICE simulation with 0.8.mu.m single-poly double-metal LG CMOS process parameter, out 16bit-ELM adder with variable-sized cells shows the reduction of power-delay-product, which is less than that of the conventional 16bit-ELM adder with reference-sized cells by 19.3%. We optimized the desin with various logic styles including static CMOs, pass-transistor logic and Wang's XOR/XNOR gate. Maximum delay path of an ELM adder depends on the implementation method of S cells and their logic style.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 1997.06a
• /
• pp.31-36
• /
• 1997

Bit allocation is a critical problem in video encoding such as MPEG. To improve the quality of the reconstructed sequence for a given bit rate, the assigned target bits for a group of pictures (GOP) must be allocated to each picture efficiently. In this paper, we derive a target bit allocation algorithm for more efficient rate control, by assuming that the average rate-distortion curve for an input source is logarithmic. This target bit allocation is based on Shannon's rate-distortion theory, which deals with the minimization of source distortion subject to a channel rate constraint. Simulation results show that the proposed target bit allocation algorithm provides better performance than the one in MPEG-2 Test Model 5 (TM5).

• Proceedings of the KIEE Conference
• /
• 1999.07g
• /
• pp.3067-3069
• /
• 1999

In this paper, A bit processor for controlling sequence logic was implemented, using a FPGA. This processor consists of program memory interface. I/O interface, parts for instruction fetch and decode, registers, ALU, program counter and etc. This FPGA is able to execute sequence instruction during program fetch cycle, because of divided bus system, program bus and data bus. Also this bit processor has instructions set that 16bit or 32bit fixed width, so instruction decoding time and data memory interface time was reduced. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package. Finally, the benchmark was performed to prove that Our FPGA has better performance than DSP(TMS320C32-40MHz) for the sequence logic control of PLC.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.22 no.4
• /
• pp.714-725
• /
• 1997

This paper proposes an image compression method using the wavelet transform and bit-plane coding of wavelet coefficients. The hierarchical application of wavelet transform to an image produces one low resoluation(the subband with lowest frequency) image and several high frequency subbands. In the proposed method, the low resolution image is compressed by a lossless method at 8 bits per each coefficient. However, the high frequency subbands are decomposed into 8 bit planes. With an adptive block coding method, the decomposed bit planes are effectively compressed using localized edge information in each bit plane. In addition, the propsoed method can control bit rates by selectively eliminating lessimportant subbands of low significant bit planes. Experimental results show that the proposed scheme has better performance in the peak signal to noise ratio (PSNR) and compression rate than conventional image coding methods using the wavelet transform and vector quantization.