• The Transactions of the Korea Information Processing Society
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• v.6 no.5
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• pp.1219-1224
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• 1999

This paper derived Montgomery's parallel algorithms for modular multiplication based on Walter's and Iwamura's method, and compared data dependence graph of each parallel algorithm. Comparing the result, Walter's parallel algorithm has small computational index in data dependence graph, so it is selected and used to computed spatial and temporal pipelining diagrams with each projection direction for designing expansible bit-level systolic array. We also evaluated internal operation of proposed expansible systolic array C++ language.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.8-16
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• 2020

In this paper, a single-bit 2nd-order delta-sigma modulator with the architecture of cascaded-of-integrator feedforward (CIFF) is proposed for column-parallel analog-to-digital converter (ADC) array used in a low noise CMOS image sensor. The proposed modulator implements two switched capacitor integrators and a single-bit comparator within only 10-㎛ column-pitch for column-parallel ADC array. Also, peripheral circuits for driving all column modulators include a non-overlapping clock generator and a bias circuit. The proposed delta-sigma modulator has been implemented in a 110-nm CMOS process. It achieves 88.1-dB signal-to-noise-and-distortion ratio (SNDR), 88.6-dB spurious-free dynamic range (SFDR), and 14.3-bit effective-number-of-bits (ENOB) with an oversampling ratio (OSR) of 418 for 12-kHz bandwidth. The area and power consumption of the delta-sigma modulator are 970×10 ㎛2 and 248 ㎼, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.632-636
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• 2006

It is needed to use the beam scanning to control the cell coverage of the base station considering operation conditions, season, time period, radiation character and mobility of customers and vehicles for varied wireless communication service and quality improvement. This paper proposes a mobile antenna system which can obtain the characteristics of the beam scanning by controlling the directivity depending on the operation condition. Radiation block is made of 2 sub-array of $1\times3$ patched antennas for ITS of 5.8GHZ bandwidth with the gain of 13dBi, and of 2 sub-array of single patched antenna for WiBro of 2.3GHZ bandwidth with the gain of 12dBi. RF module is made of a switch, an amplifier, a PAD, a 3-Bit phase shifter, and a power divider. The system is able to control the beam tilting with electronic methode by using 3-bit phase shifter$(45^{\circ},\;90^{\circ},\;180^{\circ})$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.10
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• pp.1871-1878
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• 2015

Recently, research on the Visual-MIMO by applying the concept of MIMO to communication between the LED array and camera is in progress. Although we already introduced the method for bit decision by using reference LED array pattern, it has the disadvantage of measuring the ISI each time when there is a change in the distance. To overcome this, in this paper, we propose a bit decision and error correction method used by using the luminance deviation without using the reference array pattern. First, we execute the bit decision using experimentally determined threshold. Next, we execute the error checking on the ON-LED and make a correction only if it is found to be error. Correction is determined by using the value of brightness deviation corresponding to the range of 68.2% (1) around the maximum frequency of the histogram for each ON-LED. We verify the performance of the proposed method according to the variation of ISI with distance by using both numerical and experimental analysis.

• Advances in nano research
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• v.15 no.6
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• pp.521-531
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• 2023

Quantum-dot cellular automata (QCA) has shown great potential in the nanoscale regime as a replacement for CMOS technology. This work presents a specific approach to static random-access memory (SRAM) cell based on 2:1 multiplexer, 4-bit SRAM array, and 32-bit SRAM array in QCA. By utilizing the proposed SRAM array, a single-layer 16×32-bit SRAM with the read/write capability is presented using an optimized signal distribution network (SDN) crossover technique. In the present study, an extremely-optimized 2:1 multiplexer is proposed, which is used to implement an extremely-optimized SRAM cell. The results of simulation show the superiority of the proposed 2:1 multiplexer and SRAM cell. This study also provides a more efficient and accurate method for calculating QCA costs. The proposed extremely-optimized SRAM cell and SRAM arrays are advantageous in terms of complexity, delay, area, and QCA cost parameters in comparison with previous designs in QCA, CMOS, and FinFET technologies. Moreover, compared to previous designs in QCA and FinFET technologies, the proposed structure saves total energy consisting of overall energy consumption, switching energy dissipation, and leakage energy dissipation. The energy and structural analyses of the proposed scheme are performed in QCAPro and QCADesigner 2.0.3 tools. According to the simulation results and comparison with previous high-quality studies based on QCA and FinFET design approaches, the proposed SRAM reduces the overall energy consumption by 25%, occupies 33% smaller area, and requires 15% fewer cells. Moreover, the QCA cost is reduced by 35% compared to outstanding designs in the literature.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.31-38
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• 2010

This paper presents the design of a graphic memory for QVGA-scale LCD Driver IC (LDI). The graphic memory is designed based on the pseudo-SHAM for the purpose of small area, and the memory cell structure is designed using a bit line partitioning method to improve sensing characteristics and drivabilties in the line-read operation. Also, a collision protection circuit using C-gate is designed to control collisions between read/write operations and self-refresh/line-read operations effectively. The graphic memory circuit has been designed in transistor level using $0.18{\mu}m$ CMOS technology library and the operations of the graphic memory have been verified using Hspice. The results show that the bit-bitb line voltage difference, ${\Delta}V$ increases by 40%, the charge sharing time between bit and bitb voltages $T_{CHGSH}$ decreases by 30%, and the current during line-read decreases by 40%.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.10
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• pp.1061-1070
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• 2009

In this paper, we have designed TDL(True-time Delay Line) for eliminating beam-squint occurring in active phased array antenna with large electrical size operated in wide bandwidth, and have tested its electrical performance. The proposed TDL device is composed of 4-bit microstrip delay line structure and MMIC amplifier for compensation of the delay-line loss. The measured results of gain and phase versus delay state satisfy the electrical requirements, also P1dB output power and noise figure meet the requirement. To verify the performance of fabricated TDL, we have simulated the beam patterns of wide-band active phased array antenna using the measured results and have certified the beam pattern compensation performance. As a result of simulated beam pattern compensation with respect to the 675.8 mm size antenna which is operated in X-band, 800 MHz bandwidth, we have reduced the beam squint error of ${\pm}1^{\circ}$ with ${\pm}0.1^{\circ}$. So this TDL module is able to be applied to active phase array antenna system.

• ETRI Journal
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• v.26 no.5
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• pp.413-422
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• 2004

This paper investigates the impacts of array weight errors (AWE) in an antenna array (AA) on a parallel interference cancellation (PIC) receiver in uplink synchronous and asynchronous direct sequence code division multiple access (DS-CDMA) systems. The performance degradation due to an AWE, which is approximated by a Gaussian distributed random variable, is estimated as a function of the variance of the AWE. Theoretical analysis, confirmed by simulation, demonstrates the tradeoffs encountered between system parameters such as the number of antennas and the variance of the AWE in terms of the achievable average bit error rate and the user capacity. Numerical results show that the performance of the PIC with the AA in the DS-CDMA uplink is sensitive to the AWE. However, either a larger number of antennas or uplink synchronous transmissions have the potential of reducing the overall sensitivity, and thus improving its performance.

• Bulletin of the Korean Chemical Society
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• v.14 no.2
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• pp.211-215
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• 1993

A multichannel optical detector system employing a self-scanning linear photodiode array has been developed. The photodiode array detector system is designed for various applications which require fast, multichannel detection of transient signals. The detector system consists of a controller which runs on an IBM personal computer and a detector head connected to the controller through a DB-15 cable. The entire scanning of 1024 detector elements is achieved in 20 ms. By using an on-board 16-bit counter/timer, the operational mode of the photodiode array detector is fully programmable by software. The design considerations and the performance of the photodiode array detector system is presented.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.2
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• pp.43-51
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• 1997

In this paper, we quantize the image data to simplify the systolic array architecture for block matching algorithm. As the number of bits for pixel data to be processed is reduced by quantization, one can simplify the hardware of systolic array. Especially, if the bit serial input is used, one can even more simplify the structure of processing element. First, we analize the effect of quantization to a block matching. then we show the structure of quantizer and processing element when bit serial input is used. The simulation results applied to standard images have shown that the proposed block matching method has less prediction error than the conventional high speed algorithm.