• Proceedings of the Korean Nuclear Society Conference
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• 1996.11a
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• pp.191-196
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• 1996

The potential value of the Application Specific Integrated Circuits(ASIC's) in safety systems of Nuclear Power Plants(NPP's) is being increasingly recognized because they are essentially hardwired circuitry on a chip, the reliability of the system can be proved more easily than that of software based systems which is difficult in point of software V&V(Verification and Validation). There are two types of ASIC, one is a full customized type, the other is a half customized type. PLD(Programmable Logic Device) used in this paper is a half customized ASIC which is a device consisting of blocks of logic connected with programmable interconnections that are customized in the package by end users. This paper describes the RPS(Reactor Protection System) composed of ASICs which provides emergency shutdown of the reactor to protect the core and the pressure boundary of RCS(Reactor Coolant System) in NPP's. The RPS is largely composed of five logic blocks, each of them was implemented in one PLD, as the followings. A). Bistable Logic B). Matrix Logic C).Initiation Logic D). MMI(Man Machine Interface) Logic E). Test Logic.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.63-73
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• 2004

A simple analytical model has been presented for the study of the optical bistability using a $GaAs-Al_{0.32}Ga_{0.68}As$ multiple quantum well (MQW) p-i-n diode structure. The calculation of the optical absorption is based on a semi-emperical model which is accurately valid for a range of wells between 5 and 20 nm and the electric field F< 200kV/cm . The electric field dependent analytical expression for the responsivity is presented. An attempt has been made to derive the analytical relationship between the incident optical power ( $(P_{in})$ ) and the voltage V across the device when the diode is reverse biased by a power supply in series with a load resistor. The relationship between $P_{in}$ and $P_{out}$ (i.e. transmitted optical power) is also presented. Numerical results are presented for a typical case of well size $L_Z=10.5nm,\;barrier\;size\;L_B=9.5nm$ optical wave length l = 851.7nm and electric field F? 100kV/cm. It has been shown that for the values of $P_{in}$ within certain range, the device changes its state in such a way that corresponding to every value of $P_{in}$ , two stable states and one unstable state of V as well as of $P_{out}$ are obtained which shows the optically controlled bistable nature of the device.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.425-425
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• 2012

유기물/무기물 나노 복합체를 사용하여 제작한 메모리 소자는 간단한 공정과 3차원의 고집적, 그리고 플렉서블한 특성을 가지고 있어 차세대 전자 소자 제작에 매우 유용한 소재이기 때문에 많은 연구가 진행되고 있다. 다양한 유기물 메모리 소자중에서 유기 쌍안정성 소자(organic bistable devices, OBD)의 전하 수송 메커니즘은 많이 연구가 되었지만, 트랩의 밀도와 분포에 따른 전기적 특성에 대한 연구는 미흡하다. 본 연구에서는 두 전극 사이에 나노 입자가 분산되어 있는 유기물 박막에 존재하는 트랩의 밀도와 분포로 인해 같은 인가전압에서도 다른 전도율이 나타나는 현상을 분석하였다. 하부 전극으로 Indium-tin-oxide가 코팅된 유리기판과 상부 전극인 Al 사이에 나노입자가 분산된 폴리스티렌 박막을 기억 매체로 사용하는 OBD를 제작하였다. OBD의 전기적 특성을 관찰하기 위하여 space-charge-limited-current (SCLS) 모델을 사용한 이론적인 연구를 실험 결과와 비교 분석하였다. 계산된 전류-전압 결과는 트랩 깊이에 따른 가우스 분포로 이루어진 개선된 SCLS 모델을 사용하였을 때 측정된 전류-전압 결과와 잘 일치 하였다. 낮은 인가전압에서 Ohmic 전류가 생기는 것을 개선된 SCLS 모델과 병렬저항을 사용하여 설명하였다. 이 연구 결과는 유기물/무기물 나노 복합체를 사용하여 제작한 OBD의 트랩의 밀도와 분포에 따른 전기적 특성을 이해하는데 도움을 준다.

• Korean Journal of Optics and Photonics
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• v.8 no.6
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• pp.466-470
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• 1997

We fabricated the asymmetric Fabry-Perot etalon which contains amorphous $As_2S_3$ as a spacer layer by using the method of optical multilayer coating and observed the optical bistability with the polarization. Optical thickness of the spacer layer is 2$\lambda$ at $Ar^+$ ($\lambda $=514.5 nm) laser wavelength. Optical bistability was observed at the intensities between 80~100 mW and the experiment shows us that the trends of bistable loop of the reflected and the transmitted lights are quite different depending on the state of polarization. This phenomena can be explained as the phase differences of each polarizations are different in the nonlinear Fabry-Perot etalon.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.186-186
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• 2009

Most liquid crystal display modes, including the twisted nematic (TN) $mode^1$, the in-plane switching (IPS) $mode^2$, the fringe field switching (FFS) $mode^3$, and the vertically aligned (VA) $mode^4$ are based on either a horizontal or a vertical alignment. However, for some applications, such as no-bias-bend (NBB) pi cell or bistable bend-splay display, an intermediate pretilt angle is essential$^5$. NBB pi cells have been a focus of interest because of their fast response time; however, the reliable control of the intermediate pretilt angle of liquid crystals that is required for the fabrication of NBB pi cells is challenging. The controllable pre-tilt angle of liquid crystals was investigated using a blend of horizontal and vertical polyimide prepared by a rubbing method. Various pretilt angles in the range from 0^{\circ}$ to 90^{\circ}$ were achieved as a function of the vertical polyimide content. We observed uniform liquid crystal alignment on the rubbing-treated blended polyimide layer. A NBB pi cell with an intermediate pretilt angle of 47.8^{\circ}$ was manufactured. This cell had no initial bias voltage and a low threshold voltage, which indicates that it has low power consumption. In addition, the response time of the NBB pi cell was rapid.

• KIISE Transactions on Computing Practices
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• v.23 no.6
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• pp.335-342
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• 2017

In the verification and validation procedures regarding the safety-critical software of nuclear power plants for the attainment of the requisite license from the regulatory body, it is difficult to judge the safety and dependability of the development, implementation, and validation activities through a simple reading and review of the documentation. Therefore, these activities, especially safety assurance activities, require systematic evaluation techniques to determine that software faults are acceptable level. In this study, a safety case methodology is applied in an assessment of the level and depth of the results of the development and validation of a manufacturer in its targeting of the bistable processor of a digital reactor protection system, and the evaluation results are analyzed. This study confirms the possibility of an effective supplementation of the existing safety demonstration method through the application of the employed safety case methodology.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.7
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• pp.66-79
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• 1999

We investigate the effects of high input power on the performance of optical bistable symmetric self-electooptic effect devices (S-SEEDs) using extremely shallow quantum wells (ESQWs). In this study, we consider the four ESQWs SEEDs; anti-reflection (AR)-coated ESQWs S-SEED, back-to-back AR coated ESQWs S-SEED, asymmetric F뮤교-Perot (AFP) ESQWs S-SEED, and back-to-back AFP-ESQWs S-SEED. As the input power increases, device performances such as on/off contrast ratio, on/off reflectivity difference are seriously degraded because of ohmic heating and exciton saturation. On the other hand, switching speed of the device increases up to certain value and then begins to decrease. With reasonable optimization of the input power for the best switching speed operation of the devices in a cascading optical interconnection system, we simulate and analyze the system bit-rate of the various ESQWs S-SEEDs, for a mesa of $5{\times}5{\mu}m^2$ size, changing the namber of quantum wells for the external bias of 0 V and -5V.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.3
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• pp.154-161
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• 2006

This paper describes the new types of ngative differential resistance (NDR) IC applications which use a monolithic quantum-effect device technology based on the RTD/HBT heterostructure design. As a digital IC, a low-power/high-speed MOBILE (MOnostable-BIstable transition Logic Element)-based D-flip flop IC operating in a non-return-to-zero (NRZ) mode is proposed and developed. The fabricated NRZ MOBILE D-flip flop shows high speed operation up to 34 Gb/s which is the highest speed to our knowledge as a MOBILE NRZ D-flip flop, implemented by the RTD/HBT technology. As an analog IC, a 14.75 GHz RTD/HBT differential-mode voltage-controlled oscillator (VCO) with extremely low power consumption and good phase noise characteristics is designed and fabricated. The VCO shows the low dc power consumption of 0.62 mW and good F.O.M of -185 dBc/Hz. Moreover, a high-speed CML-type multi-functional logic, which operates different logic function such as inverter, NAND, NOR, AND and OR in a circuit, is proposed and designed. The operation of the proposed CML-type multi-functional logic gate is simulated up to 30 Gb/s. These results indicate the potential of the RTD based ICs for high speed digital/analog applications.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.368-368
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• 2012

무기물 나노입자를 포함하는 유기물/무기물 나노복합체는 플렉시블 전자 소자에 적용이 가능하기 때문에 차세대 비휘발성 메모리 소자에 대한 응용연구가 활발히 진행되고 있다. 본 논문에서는 $CuInS_2$ (CIS)/ZnS 코어-쉘 나노 입자를 포함한 poly(N-vinylcarbazole) (PVK) 고분자 박막을 기억 매체로 사용하는 유기 쌍안정성 소자(organic bistable devices, OBD) 메모리 소자를 제작하고 전기적 성질에 대하여 관찰하고 전하 수송 메카니즘에 대하여 규명하였다. 화학적 방법으로 형성한 CIS/ZnS 코어-쉘 나노 입자와 PVK를 toluene 용매에 녹인 후 초음파 교반기를 사용하여 나노 복합 소재를 형성하였다. 하부 전극으로 indium-tin-oxide (ITO)가 증착되어 있는 유리 기판 위에 나노 복합 소재를 스핀코팅 방법으로 도포한 후 열을 가해 잔류 용매를 제거하였다. CIS/ZnS 코어-쉘 나노 입자가 분산되어 있는 PVK 나노 복합 소재로 구성된 박막위에 상부 전극으로 Al을 열증착하여 메모리 소자를 제작하였다. 전류-전압 (I-V) 측정 결과에서 저전압에서는 전도도가 낮은 OFF 상태를 유지하다 어느 특정 양의 전압에서 전도도가 갑자기 증가하여 높은 전도도의 ON 상태로 전이되는 쌍안정성이 관찰되었다. 전류의 ON/OFF 비율은 약 $10^3$이며 역방향 바이어스를 가해주었을 때 특정 음의 전압에서 전도도가 ON 상태에서 OFF 상태로 전환되는 전형적인 OBD 메모리 소자의 I-V 특성을 나타났다. 메모리 전하 수송 메커니즘 분석 결과 쓰기 과정은 thermionic emission (TE), space-charge-limited-current (SCLS) 모델과 지우기 과정은 Fowler-Nordheim (FN) 터널링 모델로 설명이 되었다. 제작된 소자에 대해 기억 시간 측정 결과는 ON과 OFF 상태의 전류가 장시간에도 변화가 거의 없는 소자의 안정성을 보여주었다. 이 실험 결과는 CIS/ZnS 코어-쉘 나노 입자가 분산되어 있는 PVK 나노 복합 소재를 사용하여 안정성을 가진 OBD 메모리 소자를 제작할 수 있음을 보여주고 있다.

• Nuclear Engineering and Technology
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• v.44 no.4
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• pp.421-428
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• 2012

Analog instrument and control systems in nuclear power plants have recently been replaced with digital systems for safer and more efficient operation. Digital instrument and control systems have adopted various fault-tolerant techniques that help the system correctly and safely perform the specific required functions regardless of the presence of faults. Each fault-tolerant technique has a different inspection period, from real-time monitoring to monthly testing. The range covered by each faulttolerant technique is also different. The digital instrument and control system, therefore, adopts multiple barriers consisting of various fault-tolerant techniques to increase the total fault detection coverage. Even though these fault-tolerant techniques are adopted to ensure and improve the safety of a system, their effects on the system safety have not yet been properly considered in most probabilistic safety analysis models. Therefore, it is necessary to develop an evaluation method that can describe these features of digital instrument and control systems. Several issues must be considered in the fault coverage estimation of a digital instrument and control system, and two of these are addressed in this work. The first is to quantify the fault coverage of each fault-tolerant technique implemented in the system, and the second is to exclude the duplicated effect of fault-tolerant techniques implemented simultaneously at each level of the system's hierarchy, as a fault occurring in a system might be detected by one or more fault-tolerant techniques. For this work, a fault injection experiment was used to obtain the exact relations between faults and multiple barriers of faulttolerant techniques. This experiment was applied to a bistable processor of a reactor protection system.