• 제목/요약/키워드: Binary code

검색결과 507건 처리시간 0.027초

전 영역 그레이코드 유전자 알고리듬의 효율성 증대에 관한 연구 (A Study on Computational Efficiency Enhancement by Using Full Gray Code Genetic Algorithm)

  • 이원창;성활경
    • 한국정밀공학회지
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    • 제20권10호
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    • pp.169-176
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    • 2003
  • Genetic algorithm (GA), which has a powerful searching ability and is comparatively easy to use and also to apply, is in the spotlight in the field of the optimization for mechanical systems these days. However, it also contains some problems of slow convergence and low efficiency caused by a huge amount of repetitive computation. To improve the processing efficiency of repetitive computation, some papers have proposed paralleled GA these days. There are some cases that mention the use of gray code or suggest using gray code partially in GA to raise its slow convergence. Gray code is an encoding of numbers so that adjacent numbers have a single digit differing by 1. A binary gray code with n digits corresponds to a hamiltonian path on an n-dimensional hypercube (including direction reversals). The term gray code is open used to refer to a reflected code, or more specifically still, the binary reflected gray code. However, according to proposed reports, gray code GA has lower convergence about 10-20% comparing with binary code GA without presenting any results. This study proposes new Full gray code GA (FGGA) applying a gray code throughout all basic operation fields of GA, which has a good data processing ability to improve the slow convergence of binary code GA.

실수형 Genetic Algorithm에 의한 최적 설계 (A Real Code Genetic Algorithm for Optimum Design)

  • 양영순;김기화
    • 한국전산구조공학회:학술대회논문집
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    • 한국전산구조공학회 1995년도 봄 학술발표회 논문집
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    • pp.187-194
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    • 1995
  • Traditional genetic algorithms(GA) have mostly used binary code for representing design variable. The binary code GA has many difficulties to solve optimization problems with continuous design variables because of its targe computer core memory size, inefficiency of its computing time, and its bad performance on local search. In this paper, a real code GA is proposed for dealing with the above problems. So, new crossover and mutation processes of read code GA are developed to use continuous design variables directly. The results of real code GA are compared with those of binary code GA for several single and multiple objective optimization problems. As results of comparisons, it is found that the performance of the real code GA is better than that of the binary code GA, and concluded that the rent code GA developed here can be used for the general optimization problem.

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Binary CGH를 사용한 JTC 광암호화 시스템 연구 (A study on JTC optical encryption system using binary CGHs)

  • 주성현;정만호
    • 한국광학회지
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    • 제14권5호
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    • pp.491-497
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    • 2003
  • Joint transform correlator(JTC)를 기반으로 이진 암호화 키를 사용하는 광 암호화 시스템을 제시하였다. 이진 암호화 키는 Pixel-oriented CGH의 설계방법을 이용하여 제작하였고, 컴퓨터 모의 실험결과를 통하여 구현된 이진 암호화 키의 독립성 및 효능을 조사하였다. CGH방법으로 구현된 이진 암호화 키의 효능을 검증하기 위하여 홀로그래픽 메모리 기반의 광 암호화 장치를 구성하여 실험을 하였으며 그 결과 높은 암호화 가능성을 나타내었다.

줄길이 신호원의 순환지수 부호화 (Encoding of a run-length soruce using recursive indexing)

  • 서재준;나상신
    • 전자공학회논문지A
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    • 제33A권7호
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    • pp.23-33
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    • 1996
  • This paper deals with the design of a recursively-indexed binary code for facsimile soruces and its performance. Sources used here are run-lengths of white pixels form higher-resolution facsimile. The modified huffman code used for G.3 facsimile is chosen for the performance comparison. Experiments confirm the fact that recursive indexing preserves the entropy of a memoryless geometric source: the entropy of recursively-indexed physical surce iwth roughly geometric distributin remains within 2% of the empirical source entropy. The designed recursively-indexed binary codes consist of a code applied to text-type documents and to graphics - type documents is compared iwth that of the modified huffman code. Numerical resutls show that the modified huffman code performs well for text-type documents and not equally well for graphics-tyep documents. On the other hand, recursively-indexed binary codes have shown a better performance for graphics-type documents whose distribution are similar to a geometric distribution. Specifically, the code rates of recursively-indexed binary codes with 60 codewords are from 8% to 20% of the empirical source entropy smaller than that of th emodified huffman code with 91 codewords.

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Numerical Algorithm for Phase Offsets of Binary Codes in the Code Division Multiple Access System

  • Park, Hong-Goo
    • ETRI Journal
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    • 제28권2호
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    • pp.227-230
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    • 2006
  • There has been a growing need for increased capacity in cellular systems. This has resulted in the adoption of the code division multiple access (CDMA) system as a multiple channel access method. Thus, it is important to obtain the phase offsets of binary codes in the CDMA system because distinct phase offsets of the same code are used to distinguish signals received at the mobile station from different base stations. This letter proposes an efficient algorithm to compute the phase offset of a binary code in the CDMA system through the use of the basic facts of number theory and a new notion of the subcodes of a given code. We also formulate the algorithm in a compact form.

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이원부호 위상 오프셋를 이용한 새로운 방식의 동기 획득 시스템 구현 (A New Efficient Acpuisition Method and Its Implementation using the Phase Offset of Binary Code)

  • 김동희;한영열
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1998년도 하계종합학술대회논문집
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    • pp.11-14
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    • 1998
  • This paper introuces a new efficient method of synchronization acquisition which is the most important element in DS-CDMA system using the phase offset of binary code. This approach uses the binary code function which can easily estimate the phase offset from the received spreading waveforms which respect to the receiver-stored replica of the spreading code. This paper proposes the initial acquisition model with repeat error control device that is good for perfomance. The hardware is implemented by TMS320c30

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이진 레벨 클리핑 multi-code PW-CDMA 시스템을 위한 적응역확산수신기 (Adaptive Despreading Receiver for Multi-Code PW-CDMA System with Binary-Level Clipping)

  • 최정민;이재홍
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2002년도 하계종합학술대회 논문집(1)
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    • pp.13-16
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    • 2002
  • In this paper, we propose adaptive despreading receiver for multi-code PW-CDMA system with binary-level clipping. The distortion due to clipping the multi-level signal causes the performance degradation. Adaptive despreading alleviates the effect of clipping. It is shown that the proposed adaptive despreading receiver achieves smaller BER than conventional despreading receiver for multi-code PW-CDMA system with binary-level clipping.

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실수형 Genetic-Algorithm에 의한 최적 설계 (A Real Code Genetic Algorithm for Optimum Design)

  • 양영순;김기화
    • 전산구조공학
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    • 제8권2호
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    • pp.123-132
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    • 1995
  • Genetic Algorithms(GA)는 생명체의 자연진화 법칙에 기초한 최적화 방법으로 그 범용성이 높이 평가되어지고 있다. 기존의 GA는 대부분 설계변수로 2진수형 코드를 사용하는데, 이는 실수형 설계변수로 구성된 최적화 문제를 해결하기 위해 컴퓨터 주 기억용량을 많이 사용하여야 하며, 계산 시간 면에서도 비효율적이고 또한 국부탐색 능력도 떨어지는 단점이 있다. 따라서 본 연구에서는 GA에 의한 최적화과정에서 실수형 설계변수를 직접 사용할 수 있도록 교배와 돌연변이 과정을 새로이 정식화하였다. 그리고 여러 형태의 단일 및 다목적함수 최적화 문제에 대해 실수형 GA와 2진수형 GA의 결과를 비교 검토하였다. 비교 검토 결과, 실수형 GA의 성능이 2진수형 GA보다 우수함을 알 수 있었고, 일반 최적화 방법으로 실수형 GA를 사용하여도 무방하리라 본다.

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핫스팟 접근영역 인식에 기반한 바이너리 코드 역전 기법을 사용한 저전력 IoT MCU 코드 메모리 인터페이스 구조 연구 (Low-Power IoT Microcontroller Code Memory Interface using Binary Code Inversion Technique Based on Hot-Spot Access Region Detection)

  • 박대진
    • 대한임베디드공학회논문지
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    • 제11권2호
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    • pp.97-105
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    • 2016
  • Microcontrollers (MCUs) for endpoint smart sensor devices of internet-of-thing (IoT) are being implemented as system-on-chip (SoC) with on-chip instruction flash memory, in which user firmware is embedded. MCUs directly fetch binary code-based instructions through bit-line sense amplifier (S/A) integrated with on-chip flash memory. The S/A compares bit cell current with reference current to identify which data are programmed. The S/A in reading '0' (erased) cell data consumes a large sink current, which is greater than off-current for '1' (programmed) cell data. The main motivation of our approach is to reduce the number of accesses of erased cells by binary code level transformation. This paper proposes a built-in write/read path architecture using binary code inversion method based on hot-spot region detection of instruction code access to reduce sensing current in S/A. From the profiling result of instruction access patterns, hot-spot region of an original compiled binary code is conditionally inverted with the proposed bit-inversion techniques. The de-inversion hardware only consumes small logic current instead of analog sink current in S/A and it is integrated with the conventional S/A to restore original binary instructions. The proposed techniques are applied to the fully-custom designed MCU with ARM Cortex-M0$^{TM}$ using 0.18um Magnachip Flash-embedded CMOS process and the benefits in terms of power consumption reduction are evaluated for Dhrystone$^{TM}$ benchmark. The profiling environment of instruction code executions is implemented by extending commercial ARM KEIL$^{TM}$ MDK (MCU Development Kit) with our custom-designed access analyzer.