• Title/Summary/Keyword: Bin packing

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Development of CPLD technology mapping algorithm for Sequential Circuit under Time Constraint (시간제약 조건하에서 순차 회로를 위한 CPLD 기술 매핑 알고리즘 개발)

  • Youn, Chung-Mo;Kim, Hi-Seok
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.1
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    • pp.224-234
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    • 2000
  • In this paper, we propose a new CPLD technology mapping algorithm for sequential circuit under time constraints. The algorithm detects feedbacks of sequential circuit, separate each feedback variables into immediate input variable, and represent combinational part into DAG. Also, among the nodes of the DAG, the nodes that the number of outdegree is more than or equal to 2 is not separated, but replicated from the DAG, and reconstructed to fanout-free-tree. To use this construction method is for reason that area is less consumed than the TEMPLA algorithm to implement circuits, and process time is improved rather than TMCPLD within given time constraint. Using time constraint and delay of device the number of partitionable multi-level is defined, the number of OR terms that the initial costs of each nodes is set to and total costs that the costs is set to after merging nodes is calculated, and the nodes that the number of OR terms of CLBs that construct CPLD is excessed is partitioned and is reconstructed as subgraphs. The nodes in the partitioned subgraphs is merged through collapsing, and the collapsed equations is performed by bin packing so that if fit to the number of OR terms in the CLBs of a given device. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces the number of CLBs bu 15.58% rather than the TEMPLA, and reduces process time rather than the TMCPLD.

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An Efficient CPLD Technology Mapping considering Area under Time Constraint (시간 제약 조건하에서 면적을 고려한 효율적인 CPLD 기술 매핑)

  • Kim, Jae-Jin;Kim, Hui-Seok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.1
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    • pp.79-85
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    • 2001
  • In this paper, we propose a new technology mapping algorithm for CPLD consider area under time constraint(TMFCPLD). This technology mapping algorithm detect feedbacks from boolean networks, then variables that have feedback are replaced to temporary variables. Creating the temporary variables transform sequential circuit to combinational circuit. The transformed circuits are represented to DAG. After traversing all nodes in DAG, the nodes that have output edges more than two are replicated and reconstructed to fanout free tree. This method is for reason to reduce area and improve total run time of circuits by TEMPLA proposed previously. Using time constraints and delay time of device, the number of graph partitionable multi-level is decided. Initial cost of each node are the number of OR-terms that it have. Among mappable clusters, clusters of which the number of multi-level is least is selected, and the graph is partitioned. Several nodes in partitioned clusters are merged by collapsing, and are fitted to the number of OR-terms in a given CLB by bin packing. Proposed algorithm have been applied to MCNC logic synthesis benchmark circuits, and have reduced the number of CLBs by 62.2% than those of DDMAP. And reduced the number of CLBs by 17.6% than those of TEMPLA, and reduced the number of CLBs by 4.7% than those of TMCPLD. This results will give much efficiency to technology mapping for CPLDs.

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Study of Pressure Cooling of Agricultural Products Using a Pallet Bin (팔레트 빈(pallet bin)을 이용한 농산물의 차압통풍 냉각 연구)

  • Jeong, Hoon;Yun, Hong-Sun;Lee, Hyun-Dong;Kim, Young-Keun;Lee, Won-Ok
    • Food Science and Preservation
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    • v.15 no.6
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    • pp.847-851
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    • 2008
  • The handling and processing of agricultural products in Korea is done manually. Small plastic boxes, nets, and corrugated cardboard boxes are used as containers during harvesting, sorting and other product handling operations. However, these practices are labor-intensive, time-consuming, require various kinds of packing materials, and are expensive because of high operating costs. To overcome these problems, the use of pallet bins with pre-cooling and storage features for handling and processing bulk farm products was investigated. The airflow resistances through bulk potato, onion and mandarin stocks were measured, and the pallet bins and a pressure pre-cooling device were manufactured. The opening ratio, bed depth and airflow rate through bulk potato, onion and mandarin in the pallet bin were defined with regression equations. The cooling rates of bulk potato, onion and mandarin were 0.8C/h ($21.7{\rightarrow}0C$, 14.5 h), 0.4C/h ($15.4{\rightarrow}.0C$, 32.2 h) and 0.7C/h ($13.7{\rightarrow}C$, 18.8 h), respectively, with the pressure pre-cooling system. Temperature deviances for storage of bulk potato, onion and mandarin were 0.12C, 0.12C and 0.17C, respectively.

Chromatic Number Algorithm for Exam Scheduling Problem (시험 일정 계획 수립 문제에 관한 채색 수 알고리즘)

  • Lee, Sang-Un
    • Journal of the Korea Society of Computer and Information
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    • v.20 no.4
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    • pp.111-117
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    • 2015
  • The exam scheduling problem has been classified as nondeterministic polynomial time-complete (NP-complete) problem because of the polynomial time algorithm to obtain the exact solution has been unknown yet. Gu${\acute{e}}$ret et al. tries to obtain the solution using linear programming with $O(m^4)$ time complexity for this problem. On the other hand, this paper suggests chromatic number algorithm with O(m) time complexity. The proposed algorithm converts the original data to incompatibility matrix for modules and graph firstly. Then, this algorithm packs the minimum degree vertex (module) and not adjacent vertex to this vertex into the bin $B_i$ with color $C_i$ in order to exam within minimum time period and meet the incompatibility constraints. As a result of experiments, this algorithm reduces the $O(m^4)$ of linear programming to O(m) time complexity for exam scheduling problem, and gets the same solution with linear programming.

Image-Based Machine Learning Model for Malware Detection on LLVM IR (LLVM IR 대상 악성코드 탐지를 위한 이미지 기반 머신러닝 모델)

  • Kyung-bin Park;Yo-seob Yoon;Baasantogtokh Duulga;Kang-bin Yim
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.34 no.1
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    • pp.31-40
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    • 2024
  • Recently, static analysis-based signature and pattern detection technologies have limitations due to the advanced IT technologies. Moreover, It is a compatibility problem of multiple architectures and an inherent problem of signature and pattern detection. Malicious codes use obfuscation and packing techniques to hide their identity, and they also avoid existing static analysis-based signature and pattern detection techniques such as code rearrangement, register modification, and branching statement addition. In this paper, We propose an LLVM IR image-based automated static analysis of malicious code technology using machine learning to solve the problems mentioned above. Whether binary is obfuscated or packed, it's decompiled into LLVM IR, which is an intermediate representation dedicated to static analysis and optimization. "Therefore, the LLVM IR code is converted into an image before being fed to the CNN-based transfer learning algorithm ResNet50v2 supported by Keras". As a result, we present a model for image-based detection of malicious code.

On-demand Allocation of Multiple Mutual-compensating Resources in Wireless Downlinks: a Multi-server Case

  • Han, Han;Xu, Yuhua;Huang, Qinfei
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.9 no.3
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    • pp.921-940
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    • 2015
  • In this paper, we investigate the multi-resource allocation problem, a unique feature of which is that the multiple resources can compensate each other while achieving the desired system performance. In particular, power and time allocations are jointly optimized with the target of energy efficiency under the resource-limited constraints. Different from previous studies on the power-time tradeoff, we consider a multi-server case where the concurrent serving users are quantitatively restricted. Therefore user selection is investigated accompanying the resource allocation, making the power-time tradeoff occur not only between the users in the same server but also in different servers. The complex multivariate optimization problem can be modeled as a variant of 2-Dimension Bin Packing Problem (V2D-BPP), which is a joint non-linear and integer programming problem. Though we use state decomposition model to transform it into a convex optimization problem, the variables are still coupled. Therefore, we propose an Iterative Dual Optimization (IDO) algorithm to obtain its optimal solution. Simulations show that the joint multi-resource allocation algorithm outperforms two existing non-joint algorithms from the perspective of energy efficiency.

Vehicle Loading Model Considering Routing Sequence in Shipbuilding Material (조선기자재 산업에서의 방문 순서를 고려한 차량 적재 모형)

  • Lee, Jong-Ho;Shin, Jae-Young
    • Journal of Navigation and Port Research
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    • v.31 no.8
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    • pp.711-716
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    • 2007
  • When the freight is loaded into a container loading rate must be considered. There are many studies on loading more freights into limited space. But the problem, which is needed to consider the routing sequence is different. A large size of freights, such as shipbuilding materials, am be rehandled or cannot be possible to unload. In this paper I tried to find the solution for the problem consider routing sequence, whereupon I present the container loading model which consider the routing sequence and loading rate and its solution.

A Heuristic Algorithm for Tool Loading and Scheduling in a Flexible Manufacturing System with an Automatic Tool Transporter (공구이송이 가능한 유연제조시스템에서의 공구 할당 및 스케쥴링을 위한 발견적 기법)

  • Park, Sang-Sil;Kim, Yeong-Dae
    • Journal of Korean Institute of Industrial Engineers
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    • v.21 no.1
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    • pp.119-135
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    • 1995
  • We consider problems of tool loading and scheduling in a flexible manufacturing system (FMS) in which tool transportation constitutes the major portion of material flows. In this type of FMSs, parts are initially assigned to machines and released to the machines according to input sequencing rules. Operations for the parts released to the machines are performed by tools initially loaded onto the machines or provided by an automatic tool transport robot when needed. For an efficient operation of such systems, therefore, we may have to consider loading and scheduling problems for tools in addition to those for parts. In this paper, we consider three problems, part loading, tool loading, and tool scheduling problems with the overall objective of minimizing the makespan. The part loading problem is solved by a method similar to that for the bin packing problem and then a heuristic based on the frequency of tool usage is applied for tool loading. Also suggested are part input sequencing and tool scheduling rules. To show the effectiveness of the overall algorithm suggested here, we compare it with an existing algorithm through a series of computational tests on randomly generated test problems.

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A Novel Process Design for Analyzing Malicious Codes That Bypass Analysis Techniques (분석기법을 우회하는 악성코드를 분석하기 위한 프로세스 설계)

  • Lee, Kyung-Roul;Lee, Sun-Young;Yim, Kang-Bin
    • Informatization Policy
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    • v.24 no.4
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    • pp.68-78
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    • 2017
  • Malicious codes are currently becoming more complex and diversified, causing various problems spanning from simple information exposure to financial or psychologically critical damages. Even though many researches have studied using reverse engineering to detect these malicious codes, malicious code developers also utilize bypassing techniques against the code analysis to cause obscurity in code understanding. Furthermore, rootkit techniques are evolving to utilize such bypassing techniques, making it even more difficult to detect infection. Therefore, in this paper, we design the analysis process as a more agile countermeasure to malicious codes that bypass analysis techniques. The proposed analysis process is expected to be able to detect these malicious codes more efficiently.

Water-Soluble Conjugated Polymer and Graphene Oxide Composite Used as an Efficient Hole-Transporting Layer for Organic Solar Cells (수용성 공액고분자/그래핀 옥사이드 복합체를 이용한 유기태양전지의 정공수송층에 대한 연구)

  • Kim, Kyu-Ri;Oh, Seung-Hwan;Kim, Hyun Bin;Jeun, Joon-Pyo;Kang, Phil-Huyn
    • Polymer(Korea)
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    • v.38 no.1
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    • pp.38-42
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    • 2014
  • The poly[(9,9-bis((6'-(N,N,N-trimethylammonium)hexyl)-2,7-fluorene)-alt-(9,9-bis(2-(2-(2-methoxyethoxy)ethoxy)ethyl)-9-fluorene)) dibromide (WPF-6-oxy-F)] and graphene oxide (GO) was blended and irradiated with gamma ray under ambient condition. This WPF-6-oxy-F-GO composite was investigated as a hole-transporting layer (HTL) in organic solar cells (OSCs). Compared with the pristine GO, the sheet resistance ($R_{sheet}$) of irradiated WPF-6-oxy-F-GO was decreased about 2 orders of magnitude. The reason for the decrease of $R_{sheet}$ is the effect of efficient ${\pi}-{\pi}$ packing resulted from the formation of C-N bond between WPF6-oxy-F and GO. As a result, the efficiency of OSCs was dramatically enhanced ~ 6.10% by introducing irradiated WPF-6-oxy-F-GO as a HTL. WPF-6-oxy-F-GO is a sufficient candidate for HTL to facilitate the low-cost and high efficiency OSCs.