• 전자공학회논문지A
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• 제31A권10호
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• pp.173-184
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• 1994

BiCMOS circuits mixed with CMOS and bipolar technologies show peculiar fault characteristics that are different from those of other technoloties. It has been reported that because most of short faults in BiCMOS circuits cause logically intermediate level at outputs, current monitoring method is required to detect these faluts. However current monitoring requires additional hardware capabilities in the testing equipment and evaluation of test responses can be more difficult. In this paper, we analyze the characteristics of faults in BiCMOS circuit together with their test methods and propose a new design technique for testability to detect the faults by logic monitoring. An effective method to detect the transition delay faults induced by performance degradation by the open or short fault of bipolar transistors in BiCMOS circuits is presented. The proposed design-for-testability methods for BiCMOS circuits are confirmed by the SPICE simulation.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2016년도 춘계학술대회
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• pp.696-697
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• 2016

본 논문은 5.25-GHz BiCMOS 저 잡음 증폭기를 위한 바이어스 회로를 제안한다. 이러한 회로는 1볼트 전원에서 동작하며, 저전압 및 저전력으로 동작하도록 설계되어 있다. 제안한 회로는 $0.18{\mu}m$ SiGe HBT BiCMOS로 설계하였다. 이러한 회로는 밴드 갭 참조회로 (band-gap reference circuit)를 사용하였다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제52권3호
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• pp.105-108
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• 2003

In this work, a Voltage-to-Frequency Converter(VFC) in which the output frequency is proportional to the input voltage is proposed. To obtain the temperature stable characteristics of the VFC circuit is designed by BiCMOS technology. The output frequency range is 24KHz to 65KHz and the difference between simulated and calculated values is less than about 5% for this range of output frequency. The temperature variation of sample output frequencies is less than $\pm$0.5% in the temperature range $-25^{\circ}C$ to 75$^{\circ}C$.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.1192-1195
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• 2005

This paper presents the realization of a multiple-input maximum circuit, which is operated in a current-mode. The proposed circuit operates with bi-directional input current signal and employs 5n+4 transistors for n inputs. The realization method is suitable for fabrication using CMOS technology. The proposed circuit is useful building block for the real-time systems. The performances of the proposed bi-directional maximum circuit were studied using the PSPICE analog simulation program. The simulation results verified the circuit performances are agreed with the expected values.

• 전자공학회논문지A
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• 제31A권12호
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• pp.135-141
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• 1994

A linear BiCMOS operational transconductance amplifier (OTA) is described. It consists of a CMOS linear transconductor and a bipolar translineear current gain cell followed by three CMOS current mirrors. The proposed circuit has comparable linearity and temperature stability but superior dc characteristics to its bipolar counterpart. A test circuit with a transconductance of 47.3$\mu$s has been simulated. Simulation results show that a linearity error of less than $\pm$1 percent over an input volgate range from -1.0 to 1.0 V and a output dc offset current as small as-3.6 nA can be obtained.

• 센서학회지
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• 제5권6호
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• pp.25-34
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• 1996

본 논문에서는 압저항형 압력센서를 위한 신호처리회로를 설계하였다. 신호처리회로는 압저항형 압력센서를 구동하기 위한 기준전압 회로와 미소한 센서 신호의 증폭을 위한 인스트루먼트 증폭기로 구성이 되어있다. 신호처리회로는 단일 폴리 이중 메탈(single poly double metal) $1.5\;{\mu}m$ BiCMOS 공정 파라미터를 이용하여 HSPICE로 시뮬레이션 하였다. 시뮬레이션 결과, 밴드갭 기준전압회로의 온도 계수는 $0\;{\sim}\;70^{\circ}C$의 범위에서 $21\;ppm/^{\circ}C$였고 PSRR은 80 dB였다. BiCMOS 증폭기의 이득, 옵셋, CMRR, CMR, PSRR, 특성은 CMOS나 바이폴라보다 우수하였고 전력소비 및 잡음전압 특성은 CMOS가 우수하였다. 설계한 신호처리 회로는 옵셋이 적고 입력 임피던스가 높으며 CMRR 특성이 우수하기 때문에 센서 및 계측용 신호처리회로로서 사용하기에 적합하다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1994년도 하계학술대회 논문집 C
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• pp.1460-1462
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• 1994

BiCMOS is the newly developed technology that integrates both CMOS and bipolar structures on the same integrated circuit. Improved performance can be obtained from combining the advantages of high density and low power in CMOS with the speed and current capibility advantages by bipolar. However, the major drawbacks to BiCMOS are high cost, long fabrication time and difficulty of merging CMOS with bipolar without degrading of device Performance because CMOS and bipolar share same process step. In this paper, N-Well CMOS oriented BiCMOS process and optimization of device performance are studied when N-Well links CMOS with bipolar process step by 2D process and 3D Device simulation. From the simulation, Constriction of linking process step has been understood and provided to give the method of choosing BiCMOS for various analog design request.

• 한국시뮬레이션학회논문지
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• 제11권2호
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• pp.17-29
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• 2002

There is an increasing interest in high-performance A/D(Analog-to-Digital) converters for use in integrated analog and digital mixed processing systems. Pipeline A/D converter architectures coupled with BiCMOS process technology have the potential for realizing monolithic high-speed and high-accuracy A/D converters. In this paper, the design of 12bit pipeline BiCMOS A/D converter presented. A BiCMOS operational amplifier and comparator suitable for use in the pipeline A/D converter. Test/simulation results of the circuit blocks and the converter system are presented. The main features is low distortion track-and-hold with 0-300MHz input bandwidth, and a proprietary 12bit multi-stage quantizer. Measured value is DNL=${\pm}$0.30LSB, INL=${\pm}$0.52LSB, SNR=66dBFS and SFDR=74dBc at Fin=24.5MHz. Also Fabricated on 0.8um BiCMOS process.

• 전자공학회논문지D
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• 제35D권4호
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• pp.71-77
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• 1998

In this paper, algeration of electical characteristics is analyzed when the operating temperature of MOSFET, BJT and CMOS/BiCMOS inverter is lowered from 300K to 77K. As the operating temperature is lowered, electric characteristics of MOSFET are enhanced generally but, those of bipolar transistor are degraded because current gain is reduced by BGN(Band Gap Narrowing) effect. For the inverter considered in this work, switching characteristics of PSA-BiCMOS inverter are enhanced by the electrical characteristics enhancement of MOSFET when the operating temperature is reduced to 200K, while under 200K, those of PSA-BiCMOS inverter are degraded because the degradation of BJT impacts on the inverter circuit.

• 전자공학회논문지A
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• 제33A권4호
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• pp.136-141
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• 1996

In this paper, a new CMOS on-chip current reference circit for memory, operational amplifiers, comparators, and data converters is proposed. The reference current is almost independent of temeprature and power-supply variations. In the proposed circuit, the current component with a positive temeprature coefficient cancels that with a negative temperature coefficient each other. While conventional curretn and voltage reference circuits require BiCMOS or bipolar process, the presented circuit can be integrated on a single chip with other digiral and analog circits using a standard CMOS process and an extra mask is not needed. The prototype is fabricated employing th esamsung 1.0um p-well double-poly double-metal CMOS process and the chip area is 300um${\times}$135 um. The proposed reference current circuit shows the temperature coefficient of 380 ppm/.deg. C with the temperature changes form 30$^{\circ}C$ to 80$^{\circ}C$, and the output variation of $\pm$ 1.4% with the supply voltage changes from 4.5 V to 5.5 V.