• Journal of the Korea Computer Industry Society
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• v.9 no.4
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• pp.157-170
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• 2008

In this paper, we described the Parwan(PAR-1) CPU that be developed as a reduced processor at Messachusetts Microelectronics Center using a VHDL at the behavioral level and then described by connecting CPU components at the dataflow level. Finally, we used Test-bench method to simulate and verify execution of CPU processor that was designed using a VHDL <중략> Here, Presented method was to enable information exchange of design and representation of operation were very exact and simple. Also, a documentation of design was available and it was easy that verify a operation of designed processor. The behavioral description of VHDL aids designer as we verify our understanding of the designed system, thus the dataflow description can be used to verify the bussing and register structure of the design.

• Journal of the Korea Society of Computer and Information
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• v.7 no.2
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• pp.19-33
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• 2002

In this Paper, we described the Parwan CPU using a VHDL at the behavioral level and then described by connecting CPU components at the dataflow level. Finally, we simulated to verify of execution of a CPU processor using a test-bench method. A presented design method was to enable information exchange of design and representation of operation were very exact and simple. Also. a documentation of design was available and it was easy that verify a operation of designed processor. The behavioral description of VHDL aids designer as we verify our understanding of the designed system, while the dataflow description can be used to verify the bussing and register structure of the design.

• Journal of Electrical Engineering and information Science
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• v.3 no.1
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• pp.1-7
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• 1998

High-Level synthesis of digital circuits calls for automatic translation of a behavioral description to a structural design entity represented in terms of components and connection. One of the critical steps in high-level synthesis is to determine a particular scheduling algorithm that will assign behavioral operations to control states. A new scheduling algorithm called Data Availability Scheduling (DAS) for high-level synthesis is presented. It can determine an appropriate scheduling algorithm and minimize the number of states required using data availability and dependency conditions extracted from the behavioral code, taking into account of states required using data availability and dependency conditions extracted from the behavioral code, taking into account resource constraint in each control state. The DAS algorithm is efficient because data availability conditions, and conditional and wait statements break the behavioral code into manageable pieces which are analyzed independently. The output is the number of states in a finite state machine and shows better results than those of previous algorithms.

• ETRI Journal
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• v.42 no.4
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• pp.527-533
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• 2020

High-level synthesis (HLS), which automatically synthesizes a register-transfer level (RTL) circuit from a behavioral description written in a high-level programming language such as C/C++, is becoming a more popular technique for improving design productivity. In general, HLS tools often generate a circuit with a larger area than those of hand-designed ones. One reason for this issue is that HLS tools often generate multiple instances of the same module from a function. To eliminate such a redundancy in circuit area in HLS, HLS tools are capable of sharing modules. Function-level module sharing at a behavioral description written in a high-level programming language may promote function reuse to increase effectiveness and reduce circuit area. In this paper, we present two HLS techniques for module sharing at the function level.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 1998.10a
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• pp.827-834
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• 1998

This paper describes a multi-level simulation technique and its implementation, which accurately solve voltages and currents of circuits descreibed at mixed levels of abstractions. A metho to form a tightly coupled simulation environment is proposed and, starting from a description of a circuit, simulation set-up and analysis procedure of the multi-level simulator for a transient response are presented. Circuit and behavioral simulation techniques and their implementations composing the multi-level simulation are explained in detail. Most of the algorithms implemented in the simulation are based upon the standard simulation techniques in order to obtain the reliability and accuracy of conventinoal simulators. Simulation examples show that the multi-level simulator can analyze circuits containing highly nonlinear behavioral models without loss of accuracy provided the behavioral models are accurate enough.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.135-138
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• 2005

HDL(Hardware Description Language) is the most important modem tools used to describe hardware, and becomes important as we move to higher levels of abstraction. The HDL has been made brisk use of in analog design, MEMS device[1-2], process related field as well as digital design. The most important characteristics of HDL is Abstraction which is the strongest tool that extend greatly designer's design ability. In this paper by the Modelling Continuum with hierarchical structure of abstraction, we apply UML(Unified Modeling Language) to SoC Design with HDL UML makes an easy and visual description of the various levels of abstraction, and gives designers good flexible modeling capabilty for SoC Design.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.2
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• pp.269-277
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• 1986

This paper proposes a new algorithmic state machine(ASM) chart and a new hardware description for automatic logic design of VLSI. To describe the behavioral characteristics of the design specification, the conventional ASM chart is modified, and a new hardware description language, SDL, is proposed. The SDL is one-to-one correspondent to the proposed ASM chart symbol, and can be used in a hierachical design of VLSI. As a design example, we obtain a logic circuit diagram of gate lebel utilizing a SDL hardware compiler after drawing an ASM chart and describing in SDL.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.3
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• pp.327-339
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• 1986

In this paper, a hardware compiler for symbolic description language(SDL) is proposed for logic design automation. Lexical analysis is performed for SDL which describes the behavioral characteristics of a digital system at the register transfer level by the proposed algorithm I. The algorithm I is proposed to get the expressions for the control unit and for the data transfer unit. In order to obtain the network description language(NDL) expressions equivalent to gate-level logic circuits, another algorithm, the the algorithm II, is proposed. Syntax analysis for the data formed by the algorithm I is also Performed using circuit elements such as D Flip-Flop, 2-input AND, OR, and NOT gates. This SDL hardware compiler is implemented in the programming language C(VAX-11/750(UNIX)), and its efficiency is shown by experiments with logic design examples.

• Journal of Wellbeing Management and Applied Psychology
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• v.3 no.1
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• pp.11-20
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• 2020

Anecdotal reports indicate that maladaptive patterns of Internet use constitute behavioral addiction. Internet addiction is characterized by unrestrained and awfully controlled engrossment or behaviors regarding internet access that lead to impairment, stress, dimensionally measured depression, indicators of social separation and anguish. By reviewing and analyzing approximately 100 articles we present evidence that are able to provide an overview of the main themes and proclivity covered by existing and relevant studies. The vital detection of this research unveils that many factors related to social, demographic, lifestyle changes related constructs have a bearing on the phenomenon of internet addiction strongly. This study not only reached certain conclusions for both theory and practice, but also defined future lines of research according to the gaps detected by the study's results. The main findings from this literature, though not conclusive, but will help the researcher and policymakers to obtain a better understanding and description of the problem faced by the youth and necessary to develop some remedies to lessen the addiction phenomenon.

• Journal of the Korea Society of Computer and Information
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• v.24 no.9
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• pp.59-67
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• 2019

The service composition based on Service-Oriented Architecture(SOA) can make us view various machines or its functionalities in the Web or Internet-of-Things environment as 'service', and efficiently create new value-added services that users want by compositing different services if there is no service to satisfy the client. The service composition problem with respect to behavioral descriptions deals with the automatic synthesis of a coordinator service that controls a set of services to reach a goal state. Despite its importance, however, solving the service composition problem with only partial observations remains to be doubly exponential in the number of variables in service descriptions, rendering any attempts to compute an exact solution for modest size impractical. Toward this challenge, in this paper, we propose novel approximation-based approaches using abstraction methods. We empirically validate that our proposals can solve realistic problems efficiently.