• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1774-1781
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• 1997

In this paper, we propose a full digital frequency and phase locked loop for CATV and HDTV receivers adopting VSB modulation. The CATV and HDTV receivers proposed by the Grand-Alliance in USA are ultilizing analog signal processing technology for carrier recovery. By the way, it is not a good architecture for the development of single chip ASIC operating in digital domain. To solve this problem while improving the performance, we first down convert the received r.f. signal to a near baseband signal for a low-rate AD converter and then we use digital signal processing techniques. The proposed system has the frequency pull-in range of -200 KHz +2.50 KHz. Moreover, it has the ability of adaptive loop bandwidth control according to the amount of frequency offset to improve the acquisition time while reducing the phase noise.

• Journal of IKEEE
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• v.26 no.1
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• pp.36-42
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• 2022

This study presents an analysis of the human body channel as an electric signal path using body impulse response (BIR). The human body communications (HBC) has recently emerged as an effective signal transmission method to create wireless body area networks (WBAN). We provide body channel characteristics based on measured BIR in a proper experimental environment for the HBC using capacitive coupling with a customized channel sounding device, which can be applied as a guideline for the HBC system design. The frequency response of the BIR, extracted by a customized signal processing for the measure signals, shows the channel path loss (CPS) between 0 MHz and 100 MHz with an average CPS of approximately 46.8 dB. In addition, the relative noise power distributions can provide estimations on the signal to noise ratio at the HBC receiver in terms of capacitor and resistor values in the measured frequency band and the frequency band lower than 3 MHz considering the baseband signal detection.

• Journal of Broadcast Engineering
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• v.14 no.4
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• pp.438-449
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• 2009

To analyze reception environments of ATSC Digital TV, CIR (Channel Impulse Response) analysis systems are widely applied. The receiving performances of conventional CIR analysis systems are not as good as those of commercial state-of-the-art receivers. There are difficulties in measuring and analyzing reception problems caused by multi-path interferences. To solve these problems, commercial DTV chip sets embedded CIR analysis system is proposed. Generally, commercial chip sets provide baseband (In-phase) channel data and field or segment sync data. For more precise analysis of measured I channel data, it is necessary to extract Q (quadrature) channel data components as well. This paper presents the technical requirements of CIR analysis system for DTV. In order to satisfy such requirements and measure more accurate magnitude and phase of CIR, a method to derive the quadrature data from the measured in-phase channel data is proposed. The proposed channel analysis system is implemented with a commercial DTV chip set and expedites the data analysis for use on DTV field test vehicles. Computer simulation and laboratory test results are provided to demonstrate the performance of the proposed channel analysis system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.5
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• pp.547-555
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• 2008

This parer proposed the path mismatch detection and compensation algorithm with closed form for linear amplification with non-linear components(LINC) system implementation. The LINC system has a merit of using the high efficient amplifier by transferring the non-constant envelop signal which is high peak to average signal ratio into constant envelop signal. However, the performance degradation is very sensitive to the path mismatch such as an amplitude mismatch and a phase mismatch. In order to improve the path mismatch, the error detection and compensation method is introduced by the use of four test signals. Since the presented method has the closed form solution, the efficient and fast detection is available. The digital-IF structure of LINC system applied by the proposed error detection and compensation algorithm was implemented. The performance was evaluated with the IEEE 802.16 WiMAX baseband sinal which has 7 MHz channel bandwidth and 16-QAM. The Error Vector Magnitude(EVM) of -37.37 dB was obtained through performance test, which meets performance requirement of -24 dB EVM. As a result, the introduced error detection and compensation method was verified to improve the LINC system performance.

• Journal of Space Technology and Applications
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• v.1 no.1
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• pp.33-40
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• 2021

Based on the requirements of a total weight of 42 kg or less, the NEXTSat-2 SAR (synthetic aperture radar) system was developed. As the NEXTSat-2 is a small-sized satellite, the SAR system was designed to account for about 40% of the dry mass of the payload relative to the total mass. Among the major components of the SAR system - which are an antenna, an RF transceiver, a baseband signal processor, and a power unit - a part with a particularly large dry mass is the antenna, the core of the SAR system. Whereas various selections are possible in consideration of gain and efficiency when designing the antenna, the micro-strip patch array antenna was adopted by reflecting the dry mass, power, and resolution required by the NEXTSat-2 project. In order to meet the mission requirement of the NEXTSat-2, the antenna was developed with a frequency of 9.65 GHz, a gain of 42.7 dBi, and a return loss of -15 dB. The performance of the antenna was verified by conducting a field test onboard the vehicle.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.5
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• pp.445-453
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• 2016

This paper presents the implementation and design of the 1T-1R wireless HD video streaming systems over 28 GHz mmWave frequency using 3GPP LTE-TDD standard on NI USRP RIO SDR platform. The baseband of the system uses USRP RIO that are stored in Xilinx Kintex-7 chip to implement LTE-TDD transceiver modem, the signal that are transceived from USRP RIO up or down converts to 28 GHz by using self-designed 28 GHz RF transceiver modules and it is finally communicated HD video data through self-designed $4{\times}8$ sub array antennas. It is that communication method between USRP RIO and Host PC use PCI express ${\times}4$ to minimize delay of data to transmit and receive. The implemented system show high error vector magnitude performance above 25.85 dBc and to transceive HD video in experiment environment anywhere.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.80-87
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• 2006

SONY corporation preoccupies $80\%$ of a market of the CCD used in a CCTV system. The CCD of SONY have high duality which can not follow the progress of capability. But there are some problems which differ the clock frequency used in CCD from the frequency used in common video encoder. To get the result by using common video encoder, the system needs a scaler that could adjust image size and PLL that synchronizes CCD's with encoder's clock So, this paper proposes the video encoder that is activated at equal clock used in CCD without scaler and PLL. The encoder converts ITU-R BT.601 4:2:2 or ITU-R BT.656 inputs from various video sources into NTSC or PAL signals in CVBS. Due to variable clock, property of filters used in the encoder is automatically changed by clock and filters adopt multiplier-free structures to reduce hardware complexity. The hardware bit width of programmable digital filters for luminance and chrominance signals, along with other operating blocks, are carefully determined to produce hish-quality digital video signals of ${\pm}1$ LSB error or less. The proposed encoder is experimentally demonstrated by using the Altera Stratix EP1S80B953C6ES device.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.39 no.2
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• pp.45-53
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• 2002

A wavelet-based digital watermarking algorithm is proposed that uses the successive subband quantization and human visual system (HVS). After an original image is decomposed into 4-level by the discrete wavelet transform, perceptually significant coefficients (PSC) of each subband excluding the lowest level subband are utilized to embed the watermark. PSC of the baseband ate chosen according to their amplitude and they are slightly modified to embed the watermark by a conventional embedding method. By the successive subband quantization, PSC of the high frequency subband are chosen and slightly modified according to the HVS. We tested the performance of the proposed algorithm compared with the conventional watermarking algorithm by computer simulation. Experimental results show that the proposed watermarking algorithm produces a better invisibility and robustness than the conventional algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.511-516
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• 2006

In this raper, we propose the Sequentiel Couleur Avec Memoire or Sequential Color with Memory (SECAM) video encoder system using modified anti-cloche filters and the SECAM video decoder system using a band pass filter (BPF) and an error-free square root. The SECAM encoder requires an anti-cloche filter recommended by International Telecommunication Union-Recommendation (ITU-R) Broadcasting service Television (BT) 470. However, the design of the anti-cloche filter is difficult because the frequency response of the anti-cloche filter is very sharp around rejection-frequency area. So, we convert the filter into a hish pass filter (HPF) by shifting the rejection frequency of 4.286MHz to 0Hz frequency. The design of HPF becomes very easy, compared to that of the anti-cloche filter. The proposed decoder also uses an error-free square root, two differentiators and trigonometric functions to extract color-component information of Db and Dr accurately from frequency modulation (FM) signals in SECAM systems. Also, the BPF in decoder it used for removing color noise in chrominance and dividing CVBS into chrominance and luminance. The proposed systems are experimentally demonstrated with Altera FPGA APEX20KE EP20K1000EBC652-3 device and TV sets.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.58-67
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• 2009

This paper presents a fully digital gain control system with a new high bandwidth and wide dynamic range power detector for DVB-S2 application. Because the peak-to-average power ratio (PAPR) of DVB-S2 system is so high and the settling time requirement is so stringent, the conventional closed-loop analog gain control scheme cannot be used. The digital gain control is necessary for the robust gain control and the direct digital interface with the baseband modem. Also, it has several advantages over the analog gain control in terms of the settling time and insensitivity to the process, voltage and temperature variation. In order to have a wide gain range with fine step resolution, a new AGC system is proposed. The system is composed of high-bandwidth digital VGAs, wide dynamic range power detectors with RMS detector, low power SAR type ADC, and a digital gain controller. To reduce the power consumption and chip area, only one SAR type ADC is used, and its input is time-interleaved based on four power detectors. Simulation and measurement results show that the new AGC system converges with gain error less than 0.25 dB to the desired level within $10{\mu}s$. It is implemented in a $0.18{\mu}m$ CMOS process. The measurement results of the proposed IF AGC system exhibit 80-dB gain range with 0.25-dB resolution, 8 nV/$\sqrt{Hz}$ input referred noise, and 5-dBm $IIP_3$ at 60-mW power consumption. The power detector shows the 35dB dynamic range for 100 MHz input.