• The Journal of Korea Robotics Society
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• v.4 no.1
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• pp.1-9
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• 2009

Radio Frequency Identification (RFID) is an automatic identification method. Information such as identification, logistics history, and specification of products are written and stored into the memory of RFID tags (that is, transponders), and retrieved through RF communication between RFID reader device and RFID tags. RFID systems have been applied to many fields of transportation, industry, logistics, environment, etc in order to improve business efficiency and reduce maintenance cost as well. Recently, some research results are announced in which RFID devices are combined with other sensors for mobile robot localization. In this paper, design of multi-protocol baseband for RFID reader device is proposed, and the baseband modem is implemented into SoC (System On a Chip). The baseband modem SoC for multi-protocol RFID reader is composed of several IP (Intellectual Property) blocks such as multi-protocol blocks, CPU, UART(Universal Asynchronous Receiver and Transmitter), memory, etc. As a result, the SoC implemented with FPGA(Field Programmable Gate Array) is applied to real product. It is shown that the size of RFID Reader module designed with the FPGA becomes smaller, and the SoC chip price for the same function becomes cheap. In addition, operation performance could be the same or better than that of the product with no SoC applied.

• Journal of Korea Multimedia Society
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• v.18 no.12
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• pp.1547-1554
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• 2015

Because there are numerous near field communication (NFC) technical standards and each standard has an independent communication protocol, an NFC software for controlling the protocols are significantly complicated. Especially, the anticollision algorithm for establishing the initial communication connection is classified into bit-oriented or time slot method according to the technical standards. Moreover, the anticollision algorithm is generally manipulated in software because of its complexity. In addition, since one host processor is shared by multiple modems in a connectivity SoC, embedding several communication modems with an NFC modem, the spare computing resources can be utilized for other modems by reducing the software cost to control the NFC modem. In this paper, we propose new design methods of the NFC modem for supporting anticollision, framing and bit rate detection in the hardware to reduce the software overhead. Therefore, the utilization of the NFC technology is enhanced in the connectivity SoC by minimizing the cost of software.

• Journal of Communications and Networks
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• v.13 no.1
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• pp.70-76
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• 2011

This paper presents the unified user equipment (UE) baseband modulation and demodulation (modem) hardware platform architecture to support multiple radio access technologies. In particular, this platform selectively supports two systems; one is HEDGE system, which is the combination of third generation partnership project (3GPP) Release 7 high speed packet access evolution (HSPA+) and global system for mobile communication (GSM)/general packet radio service (GPRS)/enhanced data rates for GSM evolution (EDGE), while the other is LEDGE system, which is the combination of 3GPP Release 8 long term evolution (LTE) and GSM/GPRS/EDGE. This is done by applying the flexible pin multiplexing scheme to a hardwired pin mapping process. On the other hand, to provide stable connection, high portability, and high debugging ability, the stacking structure is employed. Here, a layered board architecture grouped by functional classifications is applied instead of the conventional one flatten board. Based on this proposed configuration, we provide a framework for the verification step in wireless cellular communications. Also, modem function/scenario test and inter-operability test with various base station equipments are verified by system requirements and scenarios.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.8C
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• pp.806-813
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• 2009

This paper presents a modem chip design for high-speed wireless communications. Among the high-speed communication technologies, we design the UWB (Ultra-Wideband) modem SoC (System-on-Chip) Chip based on a MB-OFDM scheme which uses wide frequency band and gives low frequency interference to other communication services. The baseband system of the modem SoC chip is designed according to the standard document published by WiMedia. The SoC chip consists of FFT/IFFT (Fast Fourier Transform/Inverse Fast Fourier Transform), transmitter, receiver, symbol synchronizer, frequency offset estimator, Viterbi decoder, and other receiving parts. The chip is designed using 90nm CMOS (Complementary Metal-Oxide-Semiconductor) procedure. The chip size is about 5mm x 5mm and was fab-out in July 20th, 2009.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.6
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• pp.69-77
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• 2002

In this paper, we present the CDMA2000 1x compliant mobile station modem chip (SCom5010) implemented in a 0.18${\mu}{\textrm}{m}$ CMOS technology.[1] ARM940T cached processor. TeakLite DSP core, and other peripheral blocks are integrated with the baseband modem chip. Also we show novel verification methodologies and explain how this chip can be used as an emulation processor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6C
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• pp.498-504
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• 2008

In this paper, an efficient hardware platform for the digital signal processing for OFDM Communication systems is presented. The hardware platform consists of a single FPGA, two DSPs with 8000 MIPS of maximum at 1 GHz clock, 2-channel ADC and DAC supporting maximum 125 MHz sampling rate, and flexible data bus architecture, so that a wide variety of baseband signal processing algorithms for practical OFDM communication systems may be implemented and tested. The IEEE 802.16 software modem is also presented in order to verify the effectiveness and usefulness of the designed platform.