• 한국통신학회논문지
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• 제36권8B호
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• pp.1012-1020
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• 2011

분 논문에서는 해상 이동업무에 할당되어 있는 VHF 대역에서 선박과 육상간 및 선박과 선박간에 ${\pi}$/4-DQPSK 변조방법을 이용하여 디지털 데이터 및 e-mail을 교환하기 위한 기저대역 수신부 설계에 대하여 논한다 해상 통신 장치는 상대적으로 큰 주파수 불안정성을 허용하기 때문에, 상대적으로 큰 주파수 편이를 갖을 수 있는 수신 및 주파수 편이 등의 동기파라미터를 추정하고 이를 보상할 수 있는 기능을 갖도록 기저대역 수신기를 설계하였다. BER의 모의실험을 통하여 설계한 기저대역 수신기는 20% 이상의 정규화 주파수 편이가 존재하더라도 AWGN 채널환경하에서 0.5dB 이내의 성능열화가 있음을 확언 하였다.

• ETRI Journal
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• 제31권6호
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• pp.795-802
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• 2009

This paper presents the design of an advanced terrestrial digital multimedia broadcasting (AT-DMB) baseband receiver SoC. The AT-DMB baseband is incorporated into a hierarchical modulation scheme consisting of high priority (HP) and low priority (LP) stream decoders. The advantages of the hierarchical modulation scheme are backward compatibility and an enhanced data rate. The structure of the HP stream is the same as that of the conventional T-DMB system; therefore, a conventional T-DMB service is possible by decoding multimedia data in an HP stream. An enhanced data rate can be achieved by using both HP and LP streams. In this paper, we also discuss a time deinterleaver that can deinterleave data for a time duration of 384 ms or 768 ms. The interleaving time duration is chosen using the LP symbol mapping scheme. Furthermore, instead of a Viterbi decoder, a turbo decoder is adopted as an inner error correction system to mitigate the performance degradation due to a smaller symbol distance in a hierarchically modulated LP symbol. The AT-DMB baseband receiver SoC is fabricated using 0.13 ${\mu}m$ technology and shows successful operation with a 50 mW power dissipation.

• ETRI Journal
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• 제34권2호
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• pp.147-158
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• 2012

In this paper, we present a demodulation structure suitable for a reader baseband receiver in a passive radio frequency identification (RFID) environment. In a passive RFID configuration, an undesirable DC-offset phenomenon may appear in the baseband of the reader receiver, which can severely degrade the performance of the extraction of valid information from the received tag signal. To eliminate this DC-offset phenomenon, the primary feature of the proposed demodulation structures for the received FM0 and Miller subcarrier signals is to reconstruct the signal corrupted by the DC-offset phenomenon by creating peak signals from the corrupted signal. It is shown that the proposed method can successfully detect valid data, even when the received baseband signal is distorted by the DC-offset phenomenon.

• 한국ITS학회:학술대회논문집
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• 한국ITS학회 2008년도 제7회 추계학술대회 및 정기총회
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• pp.185-188
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• 2008

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권4호
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• pp.309-317
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• 2011

This paper describes a baseband analog (BBA) chain for wireless local area network (WLAN) applications. For the given specifications of the receiver BBA chain, the optimum allocation of the gain and filter rejection of each block in a BBA chain is achieved to maximize the SFDR. The fully integrated BBA chain is fabricated in 0.13 ${\mu}m$ CMOS technology. An input-referred third-order intercept point (IIP3) of 22.9 dBm at a gain of 0.5 dB and an input-referred noise voltage (IRN) of 32.2 nV/${\surd}$Hz at a gain of 63.3 dB are obtained. By optimizing the allocation of the gain and filter rejection using the proposed design methodology, an excellent SFDR performance of 63.9 dB is achieved with a power consumption of 12 mW.

• 한국전자파학회논문지
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• 제20권8호
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• pp.770-776
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• 2009

본 논문에서는 일반적인 six-port 수신기의 한 구성 성분인 BPSK 수신기와 반사형 위상 천이기를 이용하여 QPSK 신호를 복조하는 방법을 제안, 검증하고자 한다. 기존의 일반적인 곱셈 혼합 방식이나 덧셈 혼합 방식의 I/Q 복조기는 혼합기부터 parallel-to-serial 변환기까지 I/Q 경로가 분리되어 있다. 본 논문에서는 I/Q baseband 신호 경로의 분리가 없는 새로운 I/Q 복조기를 제안한다. 이는 일반적인 수신기에 비하여 baseband 경로의 회로 크기와 전력 소모를 반으로 줄일 수 있는 장점이 있다. 또한, 데이터 복조 후 parallel-to-serial 변환기가 사용될 필요가 없다. 설계된 복조기 모듈은 L-band 반송파 주파수의 데이터 율 20 Mbps까지의 QPSK 변조 신호를 성공적으로 복조하였다.

• 로봇학회논문지
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• 제4권1호
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• pp.1-9
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• 2009

Radio Frequency Identification (RFID) is an automatic identification method. Information such as identification, logistics history, and specification of products are written and stored into the memory of RFID tags (that is, transponders), and retrieved through RF communication between RFID reader device and RFID tags. RFID systems have been applied to many fields of transportation, industry, logistics, environment, etc in order to improve business efficiency and reduce maintenance cost as well. Recently, some research results are announced in which RFID devices are combined with other sensors for mobile robot localization. In this paper, design of multi-protocol baseband for RFID reader device is proposed, and the baseband modem is implemented into SoC (System On a Chip). The baseband modem SoC for multi-protocol RFID reader is composed of several IP (Intellectual Property) blocks such as multi-protocol blocks, CPU, UART(Universal Asynchronous Receiver and Transmitter), memory, etc. As a result, the SoC implemented with FPGA(Field Programmable Gate Array) is applied to real product. It is shown that the size of RFID Reader module designed with the FPGA becomes smaller, and the SoC chip price for the same function becomes cheap. In addition, operation performance could be the same or better than that of the product with no SoC applied.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2005년도 춘계학술발표대회
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• pp.1733-1736
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• 2005

본 논문에서는 기존의 설계 방법의 문제점을 해결하기 위한 설계 방법인 플랫폼 기반 설계에서 사용할 수 있는 DSP 기반 플랫폼을 구현하였다. 구현된 DSP 기반 플랫폼을 AMBA AHB 버스를 바탕으로한 듀얼프로세서 플랫폼과 crossbar switch 구조의 버스 구조를 가지고 4개의 프로세서를 연결한 멀티프로세서 플랫폼으로 확장하여 검증함으로서 이질적인 환경에서 동작함을 나타내었다. 멀티프로세서 플랫폼에서는 DVB-T baseband 수신기를 HW/SW 분할 구현하고 성능 평가를 수행하였다. DSP 기반 플랫폼은 유연성, 확장성, 고속의 연산의 특징을 가진다.

• 천문학회보
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• 제37권2호
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• pp.157.2-157.2
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• 2012

Direct-conversion receivers often suffer from a DC-offset that is a by-product of the direct conversion process to baseband. In general, a basic approach to reduce the DC-offset is to do simple average of the baseband signal and remove the DC by subtracting the average. However, this gives rise to a residual DC offset which degrades the performance when the receiver adopts the coding schemes with high coding rates such as 8-PSK. Therefore, more advanced methods should be additionally required for better performance. While the training sequences are basically designed to have good auto-correlation properties to facilitate the channel estimation, they may be not good for the simultaneous estimation of the channel response and the DC-offset. Also the DC offset compensation under a bad condition does not give good results due to the estimation error. Correspondingly, the proposed scheme employs the two important points. First, the training sequence codes are divided into two groups by MSE(Mean Squared Errors) for estimating the channel taps and then SNR calculated from each group is compared to predefined threshold to do fine DC-offset estimation. Next, ON/OFF module is applied for preventing performance degradation by large estimation error under severe channel conditions. The simulation results of the proposed scheme shows good performances compared to the existing algorithm. As a result, this scheme is surely applicable to the receiver design in many communications systems.

• 한국전자파학회논문지
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• 제13권6호
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• pp.507-513
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• 2002

본 논문에서는 헤테로다인 방식을 이용한 9.4 GHz 대역의 펄스레이다용 수신기를 설계 및 제작하였다. 펄스레이다용 헤테로다인 수신기에서 큰 부피를 차지하던 IF 증폭기를 제거하고 기저대역 부분에서 검출 로그 비디오 증폭기(Detecter logarithmic video amplifier)를 사용하여 소형화시켰으며 높은 선형 영역과 높은 수신감도를 얻도록 하였다. 측정결과, 최소수신전력 -70 dBm과 선택도 55 dB를 얻었다