• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.8B
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• pp.1012-1020
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• 2011

In this paper a design of $\pi$/4-DQPSK baseband receiver for the exchange of digital data and e-mail between shore and ship stations and/or among ship stations in the maritime mobile service VHF channels is described. Due to the permitted relatively big frequency instability of local oscillators at the transmitter and the receiver of maritime communication system, the designed baseband receiver should have the capabilities of correct estimation and compensation of the synchronization parameters, such as symbol timing and frequency offset, from the received signal which might include relatively big frequency error. Simulated BER results show that the designed baseband receiver works less than 0.5dB loss under AWGN channel when the normalized frequency offset of the received signal is more then 20%.

• ETRI Journal
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• v.31 no.6
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• pp.795-802
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• 2009

This paper presents the design of an advanced terrestrial digital multimedia broadcasting (AT-DMB) baseband receiver SoC. The AT-DMB baseband is incorporated into a hierarchical modulation scheme consisting of high priority (HP) and low priority (LP) stream decoders. The advantages of the hierarchical modulation scheme are backward compatibility and an enhanced data rate. The structure of the HP stream is the same as that of the conventional T-DMB system; therefore, a conventional T-DMB service is possible by decoding multimedia data in an HP stream. An enhanced data rate can be achieved by using both HP and LP streams. In this paper, we also discuss a time deinterleaver that can deinterleave data for a time duration of 384 ms or 768 ms. The interleaving time duration is chosen using the LP symbol mapping scheme. Furthermore, instead of a Viterbi decoder, a turbo decoder is adopted as an inner error correction system to mitigate the performance degradation due to a smaller symbol distance in a hierarchically modulated LP symbol. The AT-DMB baseband receiver SoC is fabricated using 0.13 ${\mu}m$ technology and shows successful operation with a 50 mW power dissipation.

• ETRI Journal
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• v.34 no.2
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• pp.147-158
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• 2012

In this paper, we present a demodulation structure suitable for a reader baseband receiver in a passive radio frequency identification (RFID) environment. In a passive RFID configuration, an undesirable DC-offset phenomenon may appear in the baseband of the reader receiver, which can severely degrade the performance of the extraction of valid information from the received tag signal. To eliminate this DC-offset phenomenon, the primary feature of the proposed demodulation structures for the received FM0 and Miller subcarrier signals is to reconstruct the signal corrupted by the DC-offset phenomenon by creating peak signals from the corrupted signal. It is shown that the proposed method can successfully detect valid data, even when the received baseband signal is distorted by the DC-offset phenomenon.

• 한국ITS학회:학술대회논문집
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• 2008.11a
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• pp.185-188
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• 2008

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.309-317
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• 2011

This paper describes a baseband analog (BBA) chain for wireless local area network (WLAN) applications. For the given specifications of the receiver BBA chain, the optimum allocation of the gain and filter rejection of each block in a BBA chain is achieved to maximize the SFDR. The fully integrated BBA chain is fabricated in 0.13 ${\mu}m$ CMOS technology. An input-referred third-order intercept point (IIP3) of 22.9 dBm at a gain of 0.5 dB and an input-referred noise voltage (IRN) of 32.2 nV/${\surd}$Hz at a gain of 63.3 dB are obtained. By optimizing the allocation of the gain and filter rejection using the proposed design methodology, an excellent SFDR performance of 63.9 dB is achieved with a power consumption of 12 mW.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.8
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• pp.770-776
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• 2009

We propose and demonstrate an I/Q demodulator using four-port BPSK demodulator base on additive mixing and reflection-type phase shifter using hybrid technique. Previously, the conventional I/Q demodulator base on multiplicative or additive mixing method divides I/Q signal path from mixer to parallel-to-serial converter. In this paper, we propose new I/Q demodulator without dividing I/Q baseband signal path. The proposed schematic requires half size in implementation and half power consumption in baseband path compared with the conventional receiver. Also, the proposed receiver eliminates parallel-to-serial converter after data decoding. The proposed circuit has been successfully demodulated a QPSK signal with the L-band carrier frequency and 20 Mbps data rate.

• The Journal of Korea Robotics Society
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• v.4 no.1
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• pp.1-9
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• 2009

Radio Frequency Identification (RFID) is an automatic identification method. Information such as identification, logistics history, and specification of products are written and stored into the memory of RFID tags (that is, transponders), and retrieved through RF communication between RFID reader device and RFID tags. RFID systems have been applied to many fields of transportation, industry, logistics, environment, etc in order to improve business efficiency and reduce maintenance cost as well. Recently, some research results are announced in which RFID devices are combined with other sensors for mobile robot localization. In this paper, design of multi-protocol baseband for RFID reader device is proposed, and the baseband modem is implemented into SoC (System On a Chip). The baseband modem SoC for multi-protocol RFID reader is composed of several IP (Intellectual Property) blocks such as multi-protocol blocks, CPU, UART(Universal Asynchronous Receiver and Transmitter), memory, etc. As a result, the SoC implemented with FPGA(Field Programmable Gate Array) is applied to real product. It is shown that the size of RFID Reader module designed with the FPGA becomes smaller, and the SoC chip price for the same function becomes cheap. In addition, operation performance could be the same or better than that of the product with no SoC applied.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.1733-1736
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• 2005

본 논문에서는 기존의 설계 방법의 문제점을 해결하기 위한 설계 방법인 플랫폼 기반 설계에서 사용할 수 있는 DSP 기반 플랫폼을 구현하였다. 구현된 DSP 기반 플랫폼을 AMBA AHB 버스를 바탕으로한 듀얼프로세서 플랫폼과 crossbar switch 구조의 버스 구조를 가지고 4개의 프로세서를 연결한 멀티프로세서 플랫폼으로 확장하여 검증함으로서 이질적인 환경에서 동작함을 나타내었다. 멀티프로세서 플랫폼에서는 DVB-T baseband 수신기를 HW/SW 분할 구현하고 성능 평가를 수행하였다. DSP 기반 플랫폼은 유연성, 확장성, 고속의 연산의 특징을 가진다.

• The Bulletin of The Korean Astronomical Society
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• v.37 no.2
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• pp.157.2-157.2
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• 2012

Direct-conversion receivers often suffer from a DC-offset that is a by-product of the direct conversion process to baseband. In general, a basic approach to reduce the DC-offset is to do simple average of the baseband signal and remove the DC by subtracting the average. However, this gives rise to a residual DC offset which degrades the performance when the receiver adopts the coding schemes with high coding rates such as 8-PSK. Therefore, more advanced methods should be additionally required for better performance. While the training sequences are basically designed to have good auto-correlation properties to facilitate the channel estimation, they may be not good for the simultaneous estimation of the channel response and the DC-offset. Also the DC offset compensation under a bad condition does not give good results due to the estimation error. Correspondingly, the proposed scheme employs the two important points. First, the training sequence codes are divided into two groups by MSE(Mean Squared Errors) for estimating the channel taps and then SNR calculated from each group is compared to predefined threshold to do fine DC-offset estimation. Next, ON/OFF module is applied for preventing performance degradation by large estimation error under severe channel conditions. The simulation results of the proposed scheme shows good performances compared to the existing algorithm. As a result, this scheme is surely applicable to the receiver design in many communications systems.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.6
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• pp.507-513
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• 2002

In this paper, the receiver using Heterodyne type is designed and implemented for a pulse radar at 9.4 GHz. The If amplifier, which occupies a significant size in a Heterodyne receiver for pulse radars, can be removed. Furthermore, by using detector logarithmic video amplifier in baseband, the receiver has a small size and it's characteristic shows a high dynamic range and sensitivity. From the results of measurements, the minimum receiver power of -70 dBm and selectivity of 55 dB are obtained.