• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.09a
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• pp.211-219
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• 2004

A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces stric시y related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials. In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.2
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• pp.162-172
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• 2011

In this paper, a design and fabrication of 4 W power amplifier for the WiMAX frequency band(2.3~2.7 GHz) are presented. The adopted active device is a commercially available GaN HEMT chip of Triquint Company, which is recently released. The optimum input and output impedances are extracted for power amplifier design using a specially self-designed tuning jig. Using the adopted impedances value, class-F power amplifier was designed based on EM simulation. For integration and matching in the small package module, spiral inductors and interdigital capacitors are used. The fabricated power amplifier with $4.4{\times}4.4\;mm^2$ shows the efficiency above 50 % and harmonic suppression above 40 dBc for second(2nd) and third(3rd) harmonic at the output power of 36 dBm.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2008.11a
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• pp.18-18
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• 2008

3차원 패키징 System In Package (SIP)구조에서 Chip to Chip 단위 Interconnection 역할을 하는 Through Silicon Via(TSV)를 형성하기 위하여 Pulsating RF bias가 장착된 Inductively Coupled Plasma Etcher 장비를 이용하였다. 이 Pulsating 플라즈마 공정 방법은 주기적인 펄스($50{\sim}500Hz$)와 듀티($20{\sim}99%$) cycle 조절이 가능하며, 플라즈마 에칭특성에 영향을 주는 플라즈마즈마 발생 On/Off타임을 조절할 수 있다. 예를 들면, 플라즈마 발생 Off일 경우에는 이온(SFx+, O+)과 래디컬(SF*, F*, O*)의 농도 및 활성도를 급격하게 줄이는 효과를 얻을 수가 있는데, 이러한 효과는 식각 에칭시, 이온폭격의 손상을 급격하게 줄일 수 있으며, 실리콘 표면과 래디컬의 화학적 반응을 조절하여 에칭 측벽 식각 보호막 (SiOxFy : Silicon- Oxy- Fluoride)을 형성하는데 영향을 미친다. 그리고, TSV 형성에 있어서 큰 문제점으로 지적되고 있는 언더컷과 수평에칭 (Horizontal etching)을 개선하기 위한 방법으로, Black-Siphenomenon을 이번 실험에 적용하였다. 이 Black-Si phenomenon은 Bare Si샘플을 이용하여, 언더컷(Undercut) 및 수평 에칭 (Horizontal etching)이 최소화 되는 공정 조건을 간편하게 평가 할 수 있는 방법으로써, 에칭 조건 및 비율을 최적화하는 데 효율적이었다. 결과적으로, Pulsating RF bias가 장착된 Inductively Coupled Plasma Etcher 장비를 이용한 에칭실험은 펄스 주파수($50{\sim}500Hz$)와 듀티($20{\sim}99%$) cycle 조절이 가능하여, 이온(SFx+, O+)과 래디컬(SF*, F*, O*)의 농도와 활성화를 조절 하는데 효과적이었으며, Through Silicon Via (TSV)를 형성 하는데 있어서 Black-Si phenomenon 적용은 기존의 Continuous 플라즈마 식각 결과보다 향상된 에칭 조건 및 에칭 프로파일 결과를 얻는데 효과적이었다.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2005.11a
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• pp.515-518
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• 2005

플립칩과 같은 정밀한 전자부품을 일반적인 표면실장방법에 의해 고속으로 장착 시킬 경우에는 칩의 표면이 PCB 실장면에 닿는 순간 접촉력(Contact Force)이 크게 발생한다. 과도한 접촉력에 의해 솔더 볼의 표면에 크랙이 가거나 솔더 볼이 변형되어 좁은 피치 내에서 인접해 있는 솔더 볼이 서로 붙는다든지, 또한 리드가 손상된다든지 하는 등과 같은 현상이 발생하여 표면 실장 불량의 원인이 될 가능성이 높아진다. 또한, 유연한 재질로 구성된 PCB 실장면에 과도한 힘을 가할 시에는 실장면의 국부적인 탄성변형이 발생하여 칩의 장착위치가 변경되어 정확한 위치에의 장착이 어렵게 된다. 따라서 CSP 나 플립 칩과 같은 고정도 칩을 고속으로 정확한 위치에 실장하기 위해서는 칩을 장착할 때 플립칩과 실장면의 자세를 평형상태로 제어할 필요가 있으며, 특히 발생하는 충격을 감소시키기 위한 충격 제어와 충돌 후 일정한 접촉력 유지를 할 수 있는 힘 제어가 필수적임을 알 수 있다. 따라서 본 논문에서는 상기와 같은 자세제어 및 힘제어를 요구하는 플립 칩 장착을 위한 엑츄에이터와 거리/힘 센서 시스템을 개발하였다. 제안된 시스템의 효율성을 입증하기 위해 다양한 환경에서 성능시험을 수행하였으며, 그 결과 제안된 시스템의 만족할 만한 실험결과를 보여주었다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.64.1-64.1
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• 2011

LCD 디스플레이 등에 사용되는 글래스 패널 위에 bare si die를 직접 실장하는 COG 플립칩 패키지의 경우 Au 범프와 ITO 패드 간의 전기적 접속 및 접합부 신뢰성 확보를 위해 접속소재로서 ACF (anisotropic conductive film)가 사용되고 있다. 그러나 ACF는 고가이고 접속피치 미세화에 따라 브릿지 형상에 의한 쇼트 등의 문제가 발행할 수 있어 NCP (non-conductive paste)의 상용화가 요구되고 있다. 본 연구에서는 NCP를 적용한 COG 패키지에 있어서 온도, 압력 등의 열압착 본딩 조건과 NCP 물성이 Au-ITO 접합부의 전기적 및 기계적 특성에 미치는 영향을 조사하였다. NCP는 에폭시 레진과 경화제, 촉매제를 사용하여 다양하게 포뮬레이션을 하였고 DSC (Differential Scanning Calorimeter), TGA (Thermogravimetric Analysis), DEA (Dielectric Analysis) 등의 열분석장비를 이용하여 NCP의 물성과 경화 거동을 확인하였다. 테스트 베드는 면적 $5.2{\times}7.2\;mm^2$, 두께 650 ${\mu}m$, 접속피치 200 ${\mu}m$의 Au범프가 형성된 플립칩 실리콘 다이와 접속패드가 ITO로 finish된 글래스 기판을 사용하였다. 글래스 기판과 실리콘 칩은 본딩 전 PVA Tepla사의 Microwave 플라즈마 장비로 Ar, $O_2$ 플라즈마 처리를 하였으며, Panasonic FCB-3 플립칩 본더를 사용하여 본딩하였다. 본딩 후 접합면의 보이드를 평가하고 die 전단강도로 접합강도를 측정하였다.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.91-97
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• 1998

The modulation performance of 10 Gbps electro-absorption InGaAsP/InGaAsP strain compensated MQW (Multiple Quantum Well) modulator module depends on the modulator as well as the package parasitics. The high frequency package parasitics resulting from various structural discontinuities, limit the modulation bandwidth and increase the chirp-parameter. Therefore, we propose the double bondwires embedded in dielectric materials to minimize the bondwire parasitics. Using the proposed structure with 50 $\Omega$ terminating resistor, the modulation bandwidth is greatly increased by 125 % than the bare chip and the chirp-parameter is also reduced. This technique can be used in optimizing the package of high speed external modulators.

• Journal of Biomedical Engineering Research
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• v.17 no.4
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• pp.499-506
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• 1996

Blood flow velocimeter is an essential device to measure the blood flow in skin tissue. In this study, we developed a high-speed LDV(laser Doppler Velocimeter) that has real time processing capability using a DSP(digital signal processing) chip and is able to continuously measure information about blood-flow based on a noninvasive method using self-mixing type laser diode. This LDV system has a simpler structure than any other typical blood flow velocimeter and is composed of new self-mixing probe, stabilizer circuits DSP board, and interf'ace boule We measured velocity of speaker-unit by operational frequencies to identify Doppler effect of this system, performed clinical experiment on bare finger tip and compared it with a commercial euipment BPM403A(USA).

• Journal of electromagnetic engineering and science
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• v.18 no.3
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• pp.188-198
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• 2018

In this study, we propose an approach for the design and satisfy the requirements of the fabrication of a small, lightweight, reliable, and stable ultra-wideband receiver for millimeter-wave bands and the contents of the approach. In this paper, we designed and fabricated a stable receiver with having low noise figure, flat gain characteristics, and low noise characteristics, suitable for millimeter-wave bands. The method uses the chip-and-wire process for the assembly and operation of a bare MMIC device. In order to compensate for the mismatch between the components used in the receiver, an amplifier, mixer, multiplier, and filter suitable for wideband frequency characteristics were designed and applied to the receiver. To improve the low frequency and narrow bandwidth of existing products, mathematical modeling of the wideband receiver was performed and based on this spurious signals generated from complex local oscillation signals were designed so as not to affect the RF path. In the ultra-wideband receiver, the gain was between 22.2 dB and 28.5 dB at Band A (input frequency, 18-26 GHz) with a flatness of approximately 6.3 dB, while the gain was between 21.9 dB and 26.0 dB at Band B (input frequency, 26-40 GHz) with a flatness of approximately 4.1 dB. The measured value of the noise figure at Band A was 7.92 dB and the maximum value of noise figure, measured at Band B was 8.58 dB. The leakage signal of the local oscillator (LO) was -97.3 dBm and -90 dBm at the 33 GHz and 44 GHz path, respectively. Measurement was made at the 15 GHz IF output of band A (LO, 33 GHz) and the suppression characteristic obtained through the measurement was approximately 30 dBc.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.3
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• pp.61-67
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• 2020

In this paper, we calculated the warpage of bare substrates and chip attached substrates by using FEM (Finite Element Method), and compared and analyzed the effect of the chips' attachment on warpage. Also, the effects of layer thickness of substrates for reducing warpage were analyzed and the conditions of layer thickness were analyzed by signal-to-noise ratio of Taguchi method. According to the analysis results, the direction of warpage pattern in substrates can change when chips are attached. Also, the warpage decreases as the difference in the CTE (coefficient of thermal expansion) between the top and bottom of the package decreases and the stiffness of the package increases after chips are loaded. In addition, according to the impact analysis of design parameters on substrates where chips are not attached, in order to reduce warpage, the inner layers of the circuit layer Cu1 and Cu4 has be controlled first, and then concentrated on the thickness of the solder resist on the bottom side and the thickness of the prepreg layer between Cu1 and Cu2.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.1
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• pp.65-69
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• 2008

This work shows that the grinding-induced scratches formed on the back surface of silicon chips can highly influence the flexural strength of the chips. Meanwhile, in a case that excellent adhesion between the back surface and the plastic package body maintains, the flexural strength of plastic-encapsulated packages is not so sensitive to the geometry of the scratch marks. This article explains why such different flexural fracture behavior between bare chips and plastic-encapsulated chips appears.