• Journal of Power Electronics
• /
• v.14 no.3
• /
• pp.519-530
• /
• 2014

A novel simplified pulse width modulation(PWM) strategy for neutral point clamped (NPC) three-level converter is proposed in this paper.The direct output voltage modulation is applied to reduce the calculation time. Based on this strategy, several optimized control methods are proposed. The neutral point potential balancing algorithm is discussed and a fine neutral point potential balancing scheme is introduced. Moreover, the minimum pulse width compensation and switching losses reduction can be easily achieved using this modulation strategy. This strategy also gains good results even with the unequal DC link capacitor. The modulation principle is studied in detail and the validity of this simplified PWM strategy is experimentally verified in this paper. The experiment results indicated that the proposed PWM strategy has excellent performance, and the neutral point potential can be balanced well with unequal DC link captaincies.

• Journal of Electrical Engineering and Technology
• /
• v.11 no.3
• /
• pp.629-638
• /
• 2016

This paper proposes a State-of-Charge (SOC) balancing control of Battery Power Modules (BPMs) for a modularized battery for Electric Vehicles (EVs) without additional balancing circuits. The BPMs are substituted with the single converter in EVs located between the battery and the inverter. The BPM is composed of a two-phase interleaved boost converter with battery modules. The discharge current of each battery module can be controlled individually by using the BPM to achieve a balanced state as well as increased utilization of the battery capacity. Also, an SOC balancing method is proposed to reduce the equalization time, which satisfies the regulation of a constant DC-link voltage and a demand of the output power. The proposed system and the SOC balancing method are verified through simulation and experiment.

• Journal of Power Electronics
• /
• v.18 no.1
• /
• pp.56-69
• /
• 2018

In this paper, an improved Space Vector Modulation (SVM) based fault tolerant operation on a nine-level Cascaded H-Bridge (CHB) inverter with an additional backup circuit is proposed. Any type of fault in a power converter may result in a power interruption and productivity loss. Three different faults on H-bridge modules in all three phases based on the SVM approach are investigated with diagrams. Any fault in an inverter phase creates an unbalanced output voltage, which can lead to instability in the system. An additional auxiliary unit is connected in series to the three phase cascaded H-bridge circuit. With the help of this and the redundant switching states in SVM, the CHB inverter produces a balanced output with low harmonic distortion. This ensures high DC bus utilization under numerous fault conditions in three phases, which improves the system reliability. Simulation results are presented on three phase nine-level inverter with the automatic fault detection algorithm in the MATLAB/SIMULINK software tool, and experimental results are presented with DSP on five-level inverter to validate the practicality of the proposed SVM fault tolerance strategy on a CHB inverter with an auxiliary circuit.

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.769-772
• /
• 2005

This paper describes a low-voltage and low-power channel selection analog front end with continuous-time low pass filters and highly linear programmable-gain amplifier(PGA). The filters were realized as balanced Gm-C biquadratic filters to achieve a low current consumption. High linearity and a constant wide bandwidth are achieved by using a new transconductance(Gm) cell. The PGA has a voltage gain varying from 0 to 65dB, while maintaining a constant bandwidth. A filter tuning circuit that requires an accurate time base but no external components is presented. With a 1-Vrms differential input and output, the filter achieves -85dB THD and a 78dB signal-to-noise ratio. Both the filter and PGA were implemented in a 0.18um 1P6M n-well CMOS process. They consume 3.2mW from a 1.8V power supply and occupy an area of $0.19mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.6 s.360
• /
• pp.19-27
• /
• 2007

This paper presents power supply-insensitive Gbps low power LVDS I/O circuits. The proposed LVDS I/O has been designed and simulated using 1.8V, $0.18\;{\mu}m$ TSMC CMOS Process. The LVDS I/O includes transmitter and receiver parts. The transmitter circuits consist of a differential phase splitter and an output stage with the switched capacitor common mode feedback(SC-CMFB). The differential phase splitter generates a pair of differential signals which provides a balanced duty $cycle(50{\pm}2%)$ and phase difference$(180{\pm}0.2^{\circ})$ over a wide supply voltage range. Also, $V_{OD}$ voltage is 250 mV which is the smallest value of the permissible $V_{OD}$ range for low power operation. The output buffer maintains the required $V_{CM}$ within the permissible range$(1.2{\pm}0.1V)$ due to the SC-CMFB. The receiver covers a wide input DC offset $range(0.2{\sim}2.6\;V)$ with 38 mV hysteresis and Produces a rail-to-rail output over a wide supply voltage range. Beside, the designed receiver has 38.9 dB gain at 1 GHz, which is higher than conventional receivers.