• Proceedings of the Korean Vacuum Society Conference
• /
• 1998.02a
• /
• pp.90-90
• /
• 1998

전계 에미터 어레이(FEA)는 진공에서 전계률 인가하여 전극으로부터 전자률 방출시키는 전자원으로서, 마이크로파 소자 및 명판 디스플레이, 센서 둥에 이용된다 .. Transfer Mold 법 은 뾰족한 에미터 립과 게이트 절연막 및 게이트 전극 충올 형성한 후 유리와 같은 기판에 이전 시키는 방법으로, 이러한 방법은 Mold 형태 위에 코탱 충의 두께 조절과, 게이트와 립 높이 조절이 가능하며, 그리고 유리 기판 위에 접착하여 대면적의 평판 디스플레이를 제작 할 수 었다는 장점이 있다[1,2]. 본 연구에서는 일반적으로 사용되는 실리콘 기판올 습식 식 각하여 Mold률 제작하는 방법 대선에, 측벽 스페이스 구조률 이용한 새로운 방법의 Mold 형태률 이용하여 게이트률 가진 에마터 립올 제작하였다. 먼저 실리콘 기판 위에 산화막올 증착하고 그 위에 게이트 전극파 게이트 절연막을 LPCVD 방법으로 증착하여 구명 형태로 패터닝 한 후, BPSG(Boro Phospher Silicate Glass) 박막올 증착하여 고온에서 훌러 내려 뾰족한 형태의 주형(Mold)률 제작한 후 TiN율 증착하여 정전 접합(an여ic bon벼ng)이나 레 진(resine)둥으로 유리률 접합한 후 KOH 용액으로 실리콘 기판옵 뒷면부터 식각해 낸다. 그 다옴, 립과 게이트 위에 있는 절연막올 제거한 후 뾰족한 전계 에미터 어레이륭 제조하 였다. 자세한 제조 공정 및 제작된 에미터 립의 특성은 학회에서 발표될 예정이다.

• Proceedings of the KIEE Conference
• /
• 2000.07c
• /
• pp.1620-1621
• /
• 2000

본 실험에서는 PMD Liner Nitride 공정의 최적화의 일환으로 현재 반도체 제조 공정에서 적용하고 있는 Nitride막들의 특성을 비교 분석함과 더불어 연관 공정인 BPSG 증착 및 Densification과의 관련 여부를 파악하기 위한 시도를 하였다. 특히 Nitride 박막 특성을 결정하는 중요한 요소인 Si-H 결합과 Si-NH-Si 결합의 농도 변화 분석을 위하여 FTIR Area 분석법을 이용하였다. 또한 증착된 Film의 안정성 여부를 판단하기 위하여 발생 가능한 정도의 RF Power 흔들림에 대한 Nitride 막의 Stress 변화 정도를 측정하였다.

• Korean Journal of Materials Research
• /
• v.11 no.9
• /
• pp.802-809
• /
• 2001

Electroplating is an attractive alternative deposition method for copper with the need for a conformal and conductive seed layer In addition, the Cu seed layer should be highly pure so as not to compromise the effective resistivity of the filled copper interconnect structure. This seed layer requires low electrical resistivity, low levels of impurities, smooth interface, good adhesion to the barrier metal and low thickness concurrent with coherence for ensuring void-free fill. The electrical conductivity of the surface plays an important role in formation of initial Cu nuclei, Cu nucleation is much easier on the substrate with higher electrical conductivities. It is also known that the nucleation processes of Cu are very sensitive to surface condition. In this study, copper seed layers deposited by magnetron sputtering onto a tantalum nitride barrier layer were used for electroplating copper in the forward pulsed mode. Prior to electroplating a copper film, the Cu seed layer was cleaned by plasma H$_2$ and $N_2$. In the plasma treatment exposure tome was varied from 1 to 20 min and plasma power from 20 to 140W. Effects of plasma pretreatment to Cu seed/Tantalum nitride (TaN)/borophosphosilicate glass (BPSG) samples on electroplating of copper (Cu) films were investigated.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.07a
• /
• pp.235-238
• /
• 2004

본 연구는 반도체소자 제조공정에 적용되는 CMP공정 중 LPP(Landing Plug Poly) Contact간의 소자 분리를 위해 진행되는 LPP CMP의 후 세정 과정에서 유발되는 방사형 Defect 제거에 관한 내용이다. 방사형 Defect은 LPP CMP 후에 노출되는 BPSG, Poly, Nitride Film과 연마재로 사용되는SiO2 입자, 후 세정과정에서 적용되는 SC-1, DHF, $NH_4OH$ Chemical과 Brush와의 상호작용에 의해 발생되며, Cleaning시의 산성 분위기 하에서 각 물질간의 pH와 Zeta Potential의 차이에서 기인한다. 이 Defect을 제거하기 위해 LPP CMP후에 Film 표면에 노출되는 각 물질의 표면 특성과 CMP 후 오염입자의 흡착과 재 흡착에 영향을 미치는 Electrostatic force와 Van der Waals force, PVA Brush에 의한 Mechanical force의 상호작용을 고려하여 최적 후 세정 조건을 제시 하였다.

• Korean Journal of Materials Research
• /
• v.9 no.6
• /
• pp.583-588
• /
• 1999

The characteristics of copper thin films and pattern filling capability were investigated by ECD. Prior to deposition of copper film, seed-Cu/Ta(TaN)/$SIO_2$(BPSG)/Si structure was manufactured. Copper deposition was performed with various current waveforms(DC/PC, 1~10,000Hz) and current densities(10~60 mA/$\textrm{cm}^2$) after pretreatment (Oxident removal, wetting) of seed-layer. Conformal pattern filling was performed using PC method with fast deposition rate of 6,000~8,000$\AA$/min. Heat-treated($450^{\circ}C$, 30min) copper films showed good resistivities of 1.8~2.1$\mu$$\Omega$.cm. According to the XRD analysis, (111)-preferred orientation of copper film was found in ECD-Cu/seed-Cu/Ta/$Sio_2$/Si structure. Also, we have successfully achieved to fill via holes with 0.35$\mu\textrm{m}$ width and 4:1 aspect ratio.

• Journal of the Institute of Electronics Engineers of Korea TE
• /
• v.39 no.1
• /
• pp.31-36
• /
• 2002

Low energy boron ions were implanted into the preamorphized and crystalline silicon substrates to form 0.2${\mu}m$ $p^+-n$ junctions. The rapid thermal annealing(RTA) was used to annihilate the crystal defects due to implantation and to activate the implanted boron ions, and the furnace annealing was employed to reflow the BPSG(bolo-phosphosilicate glass). The implantation conditions for Gepreamorphization were the energy of 45keV and the dose of 3$\times$1014cm-2. BF2 ions employed as a p-type dopant were implanted with the energy of 20keV and the dose of 2$\times$1015cm-2. The thermal conditions of RTA and furnace annealing were $1000^{\circ}C$/10sec and $850^{\circ}C$/40min, respectively. The junction depths were measured by SIMS and ASR techniques, and the 4-point probe was used to measure the sheet resistances. The electrical characteristics were analyzed via the leakage currents of the fabricated diodes. The single thermal processing with RTA produced shallow junctions of good qualities, and the thermal treatment sequence of furnace anneal and RTA yielded better junction characteristics than that of RTA and furnace anneal.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1996.11a
• /
• pp.71-74
• /
• 1996

Ta$_2$O$_{5}$ film ale recognized as promising capacitor dielectric for future DRAM\`s. The electrical properties of Ta$_2$O$_{5}$films greatly depend on the heating condition. In the practical fabrication process, several annealing process, such as the annealing of Al in H$_2$(about 40$0^{\circ}C$) and reflow of BPSG (borophosphosilicate glass) film in $N_2$(about 80$0^{\circ}C$), exist after deposition of Ta$_2$O$_{5}$ film. In this paper, we describe the temperature effect on the electrical properties of W/Ta$_2$O$_{5}$/Si structure. The thin film of Ta$_2$O$_{5}$ and tungsten have been deposited on p-si(100) wafer using the sputtering system. The heating temperature was varied from 500 to 90$0^{\circ}C$ in $N_2$for 30min and The degree of temperature is 100\`C. In a log(J/E$^2$) Vs 1/E plot of typical I-V data, we find a linear relationship for the temperature of 500, $600^{\circ}C$ and as deposition. This could indicate Fowler-Nordheim tunneling as the dominant mode of current transports. However, we can not find a linear relationship for the temperature above $700^{\circ}C$. This could not indicate Fowler-Nordheim tunneling as the dominant mode of current transport. The high frequency (1MHz) capacitance-voltage (C-V) of W/Ta$_2$O$_{5}$/Si Capacitor were investigated on the basis of shift in the threshold voltage and dielectric constant. The magnitude of the threshold voltage and dielectric constant depends on the heating temperature, and increases with heating temperature.temperature.