• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.3C
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• pp.287-294
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• 2010

MB-OFDM UWB system will adopt LDPC codes to enhance the decoding performance with higher data rates. In this paper, we will consider algorithm and architecture of the LDPC codes in MB-OFDM UWB system. To suggest the hardware efficient LDPC decoder architecture, LLR(log-likelihood-ration) calculation algorithms and check node update algorithms are analyzed. And we proposed the architecture of LDPC decoder for the high throughput application of Wimedia UWB. We estimated the feasibility of the proposed architecture by implementation in a FPGA. The implementation results show our architecture attains higher throughput than other result of QC-LDPC case. Using this architecture, we can implement LDPC decoder for high throughput transmission, but it is 0.2dB inferior to the BP algorithm.

• Journal of Korea Society of Digital Industry and Information Management
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• v.11 no.3
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• pp.45-51
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• 2015

In this paper, we discuss the belief propagation decoding algorithm for polar codes. The performance of Polar codes for shorter lengths is not satisfactory. Motivated by this, we propose a novel technique to improve its performance at short lengths. We showed that the probability of messages passed along the factor graph of polar codes, can be increased by multiplying the current message of nodes with their previous message. This is like a feedback path in which the present signal is updated by multiplying with its previous signal. Thus the experimental results show that performance of belief propagation polar decoder can be improved using this proposed technique. Simulation results in binary-input additive white Gaussian noise channel (BI-AWGNC) show that the proposed belief propagation polar decoder can provide significant gain of 2 dB over the original belief propagation polar decoder with code rate 0.5 and code length 128 at the bit error rate (BER) of $10^{-4}$.

• 한국정보통신설비학회:학술대회논문집
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• 2007.08a
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• pp.350-353
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• 2007

This paper presents an real-time implementation of H.264/AVC High 4:4:4 Predictive profile decoder using general-purpose processors by exploiting multi-threading technique and Single Instruction Multiple Data (SIMD) instructions without any quality degradation. We analyze differences between the existing High profile and High 4:4:4 Predictive profile decoder, and show various optimization techniques to decode high fidelity and high definition (HD) video in real-time. Simulation results show that the proposed decoder can play high fidelity HD video at average 40 frames per seconds (fps) for the IBBrBP bistream and about 50 fps for the Intra-only bitstream.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.323-326
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• 2002

In this paper, we study the improved bounds on the performance of low-density parity-check (LDPC) codes over binary-input additive white Gaussian noise (AWGN) channels with belief propagation (BP) decoding in log domain. We define an extended Gallager ensemble based on a new method of constructing parity check matrix and make use of this way to improve upper bound of LDPC codes. At the same time, many simulation results are presented in this paper. These results indicate the extended Gallager ensembles based on Hamming codes have typical minimum distance ratio, which is very close to the asymptotic Gilbert Varshamov bound and the superior performance which is better than the original Gallager ensembles.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.71-76
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• 2008

H.264(or MPEG-4/AVC pt.10) is a high performance video coding standard, and is widely used. Variable length code (VLC) of the H.264 standard compresses data using the statistical distribution of values. A decoder parses the compressed bit stream and searches decoded values in lookup tables, and the decoding process is not easy to implement by hardware. We propose an architecture of variable length decoder(VLD) for the H.264 baseline profile(BP) L4. The CAVLD decodes syntax elements using the combination of arithmetic units and lookup tables for the optimized hardware architecture. A barral shifter and a first 1's detector parse NAL bit stream, and are shared by Exp-Golomb decoder and CAVLD. A FIFO memory between CAVLD and the reorder unit and a buffer at the output of the reorder unit eliminate the bottleneck of data stream. The proposed VLD is designed using Verilog-HDL and is implemented using an FPGA. The synthesis result using a 0.18um standard CMOS technology shows that the gate count is 22,604 and the decoder can process HD($1920{\times}1080$) video at 120MHz.