• Title/Summary/Keyword: BIST(built-In self-test) circuits

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Logic Built-In Self Test Based on Clustered Pattern Generation (패턴 집단 생성 방식을 사용한 내장형 자체 테스트 기법)

  • Kang, Yong-Suk;Kim, Hyun-Don;Seo, Il-Suk;Kang, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.7
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    • pp.81-88
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    • 2002
  • A new pattern generator of BIST based on the pattern clustering is developed. The proposed technique embeds a pre-computed deterministic test set with low hardware overhead for test-per-clock environments. The test control logic is simple and can be synthesized automatically. Experimental results for the ISCAS benchmark circuits show that the effectiveness of the new pattern generator compared to the previous methods.

A New Low Power LFSR Architecture using a Transition Monitoring Window (천이 감시 윈도우를 이용한 새로운 저전력 LFSR 구조)

  • Kim Youbean;Yang Myung-Hoon;Lee Yong;Park Hyuntae;Kang Sungho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.8 s.338
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    • pp.7-14
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    • 2005
  • This paper presents a new low power BIST TPG scheme. It uses a transition monitoring window (TMW) that is comprised of a transition monitoring window block and a MUX. When random test patterns are generated by an LFSR, transitions of those patterns satisfy pseudo-random gaussian distribution. The Proposed technique represses transitions of patterns using a k-value which is a standard that is obtained from the distribution of U to observe over transitive patterns causing high power dissipation in a scan chain. Experimental results show that the Proposed BIST TPG schemes can reduce scan transition by about $60\%$ without performance loss in ISCAS'89 benchmark circuits that have large number scan inputs.