• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.1-9
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• 2006

In this paper, a couple of 10Gb/s transimpedance amplifiers are realized in a 0.18um standard CMOS technology for optical communication applications. First, the voltage-mode inverter TIA(I-TIA) exploits inverter input configuration to achieve larger effective gm, thus reducing the input impedance and increasing the bandwidth. I-TIA demonstrates $56dB{\Omega}$ transimpedance gain, 14GHz bandwidth for 0.25pF photodiode capacitance, and -16.5dBm optical sensitivity for 0.5A/W responsivity, 9dB extinction ration and $10^{-12}$ BER. However, both its inherent parasitic capacitance and the package parasitics deteriorate the bandwidth significantly, thus mandating very judicious circuit design. Meanwhile, the current-mode RGC TIA incorporates the regulated cascade input configuration, and thus isolates the large input parasitic capacitance from the bandwidth determination more effectively than the voltage-mode TIA. Also, the parasitic components give much less impact on its bandwidth. RGC TIA provides $60dB{\Omega}$ transimpedance gain, 10GHz bandwidth for 0.25pF photodiode capacitance, and -15.7dBm optical sensitivity for 0.5A/W responsivity, 9dB extinction ration and $10^{-12}$ BER. Main drawback is the power dissipation which is 4.5 times larger than the I-TIA.

• ETRI Journal
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• v.23 no.4
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• pp.199-201
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• 2001

The phase noise reduction in a configuration of the HEMT oscillator with a dielectric resonator coupled by a quarter-wavelength impedance inverter is investigated. Two HEMT oscillators for a satellite payload system are manufactured in the same configuration except for the coupling configuration of the dielectric resonator (DR) in order to empirically demonstrate the phase noise reduction. Experimental result shows that a phase noise reduction by 14 dB can be enhanced by increasing the characteristic impedance of a coupling microstrip impedance inverter.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.4
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• pp.267-272
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• 2010

In this paper, a Gm-C LPF utilizing common-mode feedforward (CMFF) CMOS inverter type operational transconductance amplifier (OTA) has been designed and verified by circuit simulations. The CMFF CMOS inverter OTA was optimized for wide input linearity and low current consumption using a standard 0.18 ${\mu}m$ CMOS process; gm of 100 ${\mu}S$ and current of 100 ${\mu}A$ at supplied voltage of 1.3 V. Using this optimized CMFF CMOS inverter type OTA, an elliptic 5th order Gm-C LPF for GPS specifications was designed. Gain and frequency tuning of the LPF was done by changing the internal supply voltages. The designed Gm-C LPF gave pass-band ripple of 1.6 dB, stop-band attenuation of 60.8 dB, current consumption of 0.60 mA at supply voltage of 1.2 V. The gain and frequency characteristics of designed Gm-C LPF was unchanged even though the input common-mode voltage is varied.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.4
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• pp.271-276
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• 2021

Arc fault detector based on multilevel DWT with analysis of high-frequency noise components over 100 kHz is proposed in this study to improve the performance in detecting serial arcs and distinguishing them from inverter noise in PV systems. PV inverters generally operate at a frequency range of 20-50 kHz for switching operation and maximum power tracking control, and the effect of these frequency components on the signal for arc detection leads to negative arc detection. High-speed ADC and multilevel DWT are used in this study to analyze frequency components above 100 kHz. Such high frequency components are less influenced by inverter noise and utilized to detect as well as separate DC series arc from inverter noise. Arc detectors identify the input current of PV inverters using a Rogowski coil. The sensed signal is filtered, amplified, and used in 800kSPS ADC and DWT analysis and arc occurrence determination in DSP. An arc detection simulation facility in UL1699B was constructed and AFD tests the proposed detector were conducted to verify the performance of arc detection and performance of distinction of the negative arc. The satisfactory performance of the arc detector meets the standard of arc detection and extinguishing time of UL1699B with an arc detection time of approximately 0.11 seconds.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.1
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• pp.76-83
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• 2000

A 2-pole tunable bandpass filter was design and fabricated using ceramic coaxial resonators and varactor diodes for UHF band. By inspection of frequency characteristics of the T-and $\pi$-type inverter equivalent circuits, we can design a two-pole tunable BPF with only two varactors. The measured data of the filter show 800 MHz-900 MHz tunable center frequency range, 4.5 dB insertion loss, 0.5 dB passband ripple and at least 15 dB return loss, which agree well with the simulated results.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.39-46
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• 2016

This paper describes the third order feedforward delta-sigma modulator with inverter-based integrators and a 1.5bit comparator for the application of audio signal processing. The proposed 3rd-order delta-sigma modulator is multi-bit structure using 1.5 bit comparator instead of operational amplifier. This delta-sigma modulator has high SNR compared with single-bit 4th-order delta-sigma modulator in a low OSR. And it minimizes power consumes and simplified circuit structure using inverter-based integrator and using inverter-based integrator as analogue adder. The modulator was designed with 0.18um CMOS standard process and total chip area is $0.36mm^2$. The measured power cosumption is 28.8uW in a 0.8V analog supply and 66.6uW in a 1.8V digital supply. The measurement result shows that the peak SNDR of 80.7 dB, the ENOB of 13.1bit and the dynamic range of 86.1 dB with an input signal frequency of 2.5kHz, a sampling frequency of 2.56MHz and an oversampling rate of 64. The FOM (Walden) from the measurement result is 269 fJ/step, FOM (Schreier) was calculated as 169.3 dB.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.52 no.7
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• pp.352-360
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• 2003

This paper deals with a simple method in order to analyze and compare the harmonic characteristics in the multi-level inverter. Generally, the magnitude of harmonic components becomes different according to the multi-carrier Pulse Width Modulation(PWM) techniques, the modulation index($M_i$) and the switching frequency The previous papers analyzed the harmonic characteristics from the viewpoint of the space voltage vector. Hence, the calculation of the harmonic vector becomes more difficult and complex in 4-level or over 5-level. However, the proposed method has reduced an amount of calculation and simplified the process of it, using the relationship between the reference voltage and the output phase voltage to the load neutral point. It is applied to the 5-level cascade inverter and the harmonic characteristics for each multi-carrier PWM technique are compared through the simulation.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.52 no.4
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• pp.161-169
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• 2003

The applications of SRM(Switched Reluctance motor) are dramatically increasing due to a simple mechanical structure, a high efficiency and a high speed drive characteristics. Energy recovery in the regenerative region is very important when SRM is used in traction drive. This is to reduce energy loss during mechanical braking and/or to have a high efficiency drive. To control excitation voltage during motoring and regenerating voltage in the generator operation in the SRM, multi-level voltage control is effective. This paper suggests multi-level inverter which is useful for motoring and regenerative operation. The proposed method is verified through simulations and experiments.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.21 no.10
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• pp.1262-1272
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• 1997

An experimental study on the frequency control of an inverter heat pump to get the desired indoor room temperature has been conducted for the performance characteristics during the steady, 4, 8, and 16 step frequency operations. The heat pump model used in this study was operated to meet the experimental conditions of ASHRAE standard. The performance of the system was tested by measuring the temperature and pressure of the refrigerant, and cooling capacity, power consumption, etc. of the system. As the controlling frequency steps increased, the running time of the compressor increased as well as the electric consumption of the system and the cooling energy due to the wall heating load. However, the average cooling COP was improved.

• Proceedings of the KIPE Conference
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• 2001.07a
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• pp.352-355
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• 2001

This paper makes a general description of the results at government project which were peformed for several years. Through this project, the real capacity of 3.3KV/4MW Class 3 Level Voltage Source Inverter System were designed and the characteristics of its proto type were analyzed, moreover the web based IIMS(Inverter Information Management System) and Virtual Operation Simulator was developed. Now, this system is running for field application test.