• Journal of IKEEE
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• v.19 no.3
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• pp.357-365
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• 2015

Recently, embedded systems such as aircraft and automobilie, are developed as modular architecture instead of federated architecture because of SWaP(Size, Weight and Power) issues. In addition, partition operating system that support multiple logical node based on partition concept were recently appeared. Distributed recovery block is fault tolerance design scheme that applicable to mission critical real-time system to support real-time take over via real-time synchronization between participated nodes. Because of real-time synchronization, single-core based computer is not suitable for partition based distributed recovery block design scheme. Multi-core and AMP(Asymmetric Multi-Processing) based partition architecture is required to apply distributed recovery block design scheme. In this paper, we proposed design scheme of distributed recovery block on the multi-core based supervised-AMP architecture partition operating system. This paper implements flight control simulator for avionics to check feasibility of our design scheme.

• Journal of Aerospace System Engineering
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• v.13 no.5
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• pp.1-8
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• 2019

Recently, avionics has been migrating from a federated architecture to an integrated modular architecture based on a multi-core to reduce the number of systems, weight, power consumption, and platform redundancy. The volume of data which must bo provided to the pilot through the display device has increased, because an integrated single device performs multiple functions. For this reason, the volume of data processed by the graphic processor within a fixed operation period has increased. In this paper, we provide a multi-core-based rendering engine in to perform more graphics processing within a fixed operation period. We assume the proposed method uses a multi-core-based partitioning operating system using the AMP (Asymmetric Multi-Processing) architecture.

• Journal of Advanced Navigation Technology
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• v.19 no.5
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• pp.423-432
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• 2015

This paper shows that design, manufacture and the performance of FC-NIC (fibre channel network interface card) for network unit configuration which is based on one of the 5 main configuration items of the common functional module for IMA (integrated modular Avionics) architecture. Especially, FC-NIC uses zynq SoC (system on chip) for host load reductions. The host merely transmit FC destination address, source memory location and size information to the FC-NIC. After then the FC-NIC read the host memory via DMA (direct memory access). FC upper layer protocol and sequence process at local processor and programmable logic of FC-NIC zynq SoC. It enables to free from host load for external communication. The performance of FC-NIC shows average 5.47 us low end-to-end latency at 2.125 Gbps line speed. It represent that FC-NIC is one of good candidate network for IMA.

• Journal of the Korea Institute of Military Science and Technology
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• v.14 no.2
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• pp.213-221
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• 2011

Avionics system tends to be designed to have the integrated architecture, and it is getting difficult and complex to verify the flight-critical function because of sophisticated structure. In Korean Utility Helicopter, mission computer acts as the MUX Bus Controller to handle the data from both communication, identification, mission/display and survivability equipment inside Mission Equipment Package and aircraft subsystems such as fuel system and electrical system while it is interfacing with Automatic Flight Control System and Full-Authority Digital Engine Control via ARINC-429 bus. The Flight Displays which is classified as flight-critical function in aircraft is implemented on Primary Flight Display after mission computer processes data from AFCS in order to generate graphics. This paper defines the flight-critical function implemented in mission computer for KUH, and presents the static and dynamic test procedures which is performed on System Integration Laboratory along with Playback Recorder prior to flight test.

• Journal of Advanced Navigation Technology
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• v.28 no.4
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• pp.393-399
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• 2024

The digital map computer for advanced air vehicles (AAV) must be high-performance, lightweight, portable, and modular. It should receive data on terrain, weather, and obstacles from external modules to display digital maps accurately. This necessitates robust communication capabilities with external devices via an Ethernet interface and the ability to output digital map visuals clearly through an high-defintion multimedia Interface (HDMI) or digital visual interface (DVI) interface. This paper presents the design of both hardware and software architecture that fulfills these critical requirements for an AAV digital map system. Additionally, it establishes the minimum specifications needed and verifies the suitability of the designed digital map computer through rigorous performance measurements and testing. By ensuring these standards, the digital map computer can reliably support the complex navigational needs of AAV, enhancing operational efficiency and safety.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.11
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• pp.1088-1093
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• 2014

The structure of the fire control system(FCS) of a light armed helicopter and effective logistics support was taken into account in the proposed common weapon interface module(CWIM) for a distributed FCS. The pros and cons of a distributed FCS and a centralized FCS were analyzed, then a CWIM which can be applied to the weapon interface module of a distributed FCS was designed and fabricated. Integration tests between the proposed CWIM and a weapon simulator were conducted to ascertain whether or not the proposed CWIM could be applicable to a distributed FCS. We expect that the CWIM design approach method secured through this study will be helpful in mitigating cable work of the FCS which will be applied to a Light Armed Helicopter and controlling various weapons.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.30 no.7
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• pp.144-149
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• 2002

This paper presents a technique for real time multiprocessor parallel processing to develop an avionic system computer(ASC) which integrates the avionics control, navigation and fire control, cursive and raster graphic symbol generation into one line replaceable unit. The proposed method has optimal performance by adopting a logically asymmetric structure between four 32bit RISC processors based on the master-slave multiprocessing, a tightly coupled interaction level with the time shared common bus and global memory, and an efficient bus arbitration algorithm. The ASC has been verified through a series of flight tests. The relevant tests also have been rigorously conducted on the prototype ASC such as electrical test, environmental test, and electromagnetic interference test.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.50 no.4
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• pp.259-267
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• 2022

The existing method of deriving the fail-safe design requirements for the domestic developed rotary-wing aircraft system may miss the factors that cause critical system function failures, when being applied to the latest integrated avionics system. It is because the existing method analyzes the severity effect of the failures caused by a single item. To solve the issue, we present a systematic analysis procedure for deriving fail-safe design requirements of system architecture by utilizing functional hazard assessment and development assurance level analysis of SAE ARP4754A, international standard for complex system development. To demonstrate that our proposed procedure can be a solution for the aforementioned issue, we set up experimental environments that include common factors that can cause critical function failures of a system, and we conducted a cross-validation with the existing method. As a result, we showed that the proposed procedure can identify the potential critical common factors that the existing method have missed, and that the proposed procedure can derive fail-safe design requirements to control the common factors.